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A multi- -layer layer A multi A multi-layer research and - - PowerPoint PPT Presentation

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Final Workshop of CDC 2002-2007 Tallinn, Brotherhood of the Blackheads, 21 22 January 2008 A multi- -layer layer A multi A multi-layer research and training platform research and training platform research and training platform for

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Department of Computer Engineering Tallinn University of Technology Estonia

Final Workshop of CDC 2002-2007 Tallinn, Brotherhood of the Blackheads, 21 – 22 January 2008

A multi-layer research and training platform for system-on-chip testing:

Hardware, Software and Web Interface

A multi A multi-

  • layer

layer research and training platform research and training platform for system for system-

  • on
  • n-
  • chip testing:

chip testing:

Hardware, Software and Web Interface Hardware, Software and Web Interface

Artur ur Artur ur Jutman an Jutman an

  • Dept. of Computer Engineering

Tallinn University of Technology Estonia

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A multi-layer research and training platform for system-on-chip testing

Outline

Introduction and motivation Different layers of the platform HW tools PC-based tools Web interface E-Learning tools Conclusions and discussion

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A multi-layer research and training platform for system-on-chip testing

Motivation

Cutting Edge Research

−Needs custom developed algorithms

and/or tools

PhD Students

−Need to run their experiments

Undergraduate Students

−Need introduction to the topic

Department

−Needs training materials and research

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A multi-layer research and training platform for system-on-chip testing

Different layers of the platform

Web Tools PC Tools Hardware Tools

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A multi-layer research and training platform for system-on-chip testing

Main components of the platform

DefSim - an integrated measurement environment for physical defect study in CMOS circuits. TurboTester – a research and training toolkit with extensive set of tools for digital test and design for testability Web-based runtime interface for remote access to our tools Java applets – illustrative e-learning software written specifically for the web Other tools

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A multi-layer research and training platform for system-on-chip testing

Different layers of the platform

Web Tools PC Tools Hardware Tools

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A multi-layer research and training platform for system-on-chip testing

Defect Study using DefSim

DefSim is an integrated circuit (ASIC) and a measurement equipmrnt for experimental study of CMOS defects. The central element of the DefSim equipment is an educational IC with a large variety of shorts and opens physically inserted into a set of simple digital circuits. The IC is attached to a dedicated measurement box serving as an interface to the computer. The box supports two measurement modes - voltage and IDDQ testing. http://www.defsim.com

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A multi-layer research and training platform for system-on-chip testing

− Standard industrial CMOS

technology

− Area 19.90 mm2 − Approx. 48000

transistors

− 62 pins − JLCC68 package

A built A built-

  • in current monitor

in current monitor for for I IDDQ

DDQ testing

testing is is implemented in each block. implemented in each block.

DefSim IC details

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A multi-layer research and training platform for system-on-chip testing

NAND2 cell with floating gate NAND2 cell with floating gate

VDD GND Q A B

X

Implementation of defects

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A multi-layer research and training platform for system-on-chip testing

VDD GND Q A B

NAND2 cell with D NAND2 cell with D-

  • S short (missing poly)

S short (missing poly)

  • Altogether there are over 500

different defects on the chip

  • Implemented defects are shorts

and opens in metal and poly layers

  • To be close to the silicon reality

each cell is loaded and driven by standard non-inverting buffers

Implementation of defects

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A multi-layer research and training platform for system-on-chip testing

DefSim in the classroom

With DefSim you can

Observe the truth table of correct circuit Observe the truth table of defective circuit Obtain defect/fault tables for all specific defects Define test patterns automatically or manually Activate IDDQ and voltage measurements Study behavior of bridging and open faults Study and compare different fault models

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A multi-layer research and training platform for system-on-chip testing

“Plug and Play” – dedicated hardware and software

DefSim lab environment

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A multi-layer research and training platform for system-on-chip testing

DefSim user interface

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A multi-layer research and training platform for system-on-chip testing

Different layers of the platform

Web Tools PC Tools Hardware Tools

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A multi-layer research and training platform for system-on-chip testing

Used in 100+ institutions in 47 countries

Design Error Diagnosis Test Generators BIST Emulator Design Test Set Levels: Gate Macro RTL Fault Table Test Set Optimizer Methods: BILBO CSTP Hybrid Faulty Area Circuits: Combinational Sequential Logic Simulator Formats: EDIF AGM Defect Library Hazard Analysis Data Specifi- cation Algorithms: Deterministic Random Genetic Multivalued Simulator Fault models: Stuck-at faults Physical defects Fault Simulator

http://www.pld.ttu.ee/tt

PC-Based Toolkit – Turbo Tester

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A multi-layer research and training platform for system-on-chip testing

http://www.pld.ttu.ee/tt

Turbo Tester’s user interface

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A multi-layer research and training platform for system-on-chip testing

  • Freeware

Freeware

  • Downloadable via the Web

Downloadable via the Web

  • Windows, Linux, UNIX/Solaris

Windows, Linux, UNIX/Solaris

  • EDIF design interface

EDIF design interface

  • ATPGs

ATPGs, BIST, simulators, test , BIST, simulators, test compaction compaction

  • Provides homogeneous environment

Provides homogeneous environment for research and training for research and training

Turbo Tester: Basic Facts

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A multi-layer research and training platform for system-on-chip testing

Different layers of the platform

Web Tools PC Tools Hardware Tools

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A multi-layer research and training platform for system-on-chip testing

BIST Analyzer: covered topics

Test Pattern Generators (PRPG):

−LFSR −Modular LFSR −Cellular Automata −GLFSR −Weighted TPG −etc.

Combined Techniques (PRPG + Memory):

−Reseeding −Multiple polynomial BIST −Hybrid BIST −Bit-Flipping BIST −Column matching BIST −etc.

BIST Control Unit Circuit Under Test (CUT) Test Pattern Generator (PRPG)

........

........

Output Response Analyzer (MISR) BIST Memory

Typical BIST Architecture

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A multi-layer research and training platform for system-on-chip testing

  • Different embedded generators (PRPG) and

their properties

  • PRPG optimization methodologies and

algorithms

  • Mixed-mode BIST solutions (PRPG+memory)
  • Fault detection and diagnosis in BIST

BIST Analyzer: covered topics

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A multi-layer research and training platform for system-on-chip testing

BIST Analyzer

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A multi-layer research and training platform for system-on-chip testing

Different layers of the platform

Web Tools PC Tools Hardware Tools

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A multi-layer research and training platform for system-on-chip testing

Web Interface

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A multi-layer research and training platform for system-on-chip testing

Different layers of the platform

Web Tools PC Tools Hardware Tools

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A multi-layer research and training platform for system-on-chip testing

E-Learning software on DFT

http://www.pld.ttu.ee/applets

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A multi-layer research and training platform for system-on-chip testing

Essential supplement to the university lectures Accessibility over Internet Visual content Comprehensive examples Better organization of teaching materials Based on free educational software Distance learning & computer aided teaching Easy to implement in other universities Constantly updated

Benefits of e-learning software

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A multi-layer research and training platform for system-on-chip testing

Test Generation Error Diagnosis Built-In Self-Test Design for Testability Test and Diagnostics RTL Design and Test Boundary Scan Applet on Basics

  • f Test &

Diagnostics Applet on RTL Design and Test Applet on Boundary Scan Standard Schematic & DD Editor Turbo Tester Group of Applets on FSM Decomposition

E-Learning Software

Java Applets Turbo Tester

Scenario 4 Scenario 4 Design for Design for Testability Testability Scenario 3 Scenario 3 Built Built-

  • In

In Self Self-

  • Test

Test Scenario 2 Scenario 2 Error Error Diagnosis Diagnosis Scenario 1 Scenario 1 Test Test Generation Generation Scenario 4 Scenario 4 Design for Design for Testability Testability Scenario 3 Scenario 3 Built Built-

  • In

In Self Self-

  • Test

Test Scenario 2 Scenario 2 Error Error Diagnosis Diagnosis Scenario 1 Scenario 1 Test Test Generation Generation

Supporting Materials Learning Scenarios

Web based tools for classroom, home and exams Tools for laboratory research

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A multi-layer research and training platform for system-on-chip testing

E-Learning Software

Logic level diagnostics System level test & DfT

Software for classroom, home, labs and exams:

http://www.pld.ttu.ee/applets Boundary Scan

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A multi-layer research and training platform for system-on-chip testing

  • manual test pattern generation assisted by the applet
  • generation of pseudo-random test vectors by LFSR
  • fault simulation & study of fault table
  • combinational fault diagnosis using fault tables
  • sequential fault diagnosis by guided probing

Applet on basics of test

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A multi-layer research and training platform for system-on-chip testing

  • design of a data path and control path (microprogram) on RT level
  • investigation of tradeoffs between speed of the system & HW cost
  • RT-level simulation and validation
  • gate-level deterministic test generation and functional testing
  • fault simulation
  • logic and circular BIST, functional BIST, etc.
  • design for testability

Applet on RT-level design and test

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A multi-layer research and training platform for system-on-chip testing

  • Simulation of operation of TAP Controller

Simulation of operation of TAP Controller

  • Illustration of work of BS registers

Illustration of work of BS registers

  • Insertion and diagnosis of interconnection faults

Insertion and diagnosis of interconnection faults

  • Design/editing of BS structures using the BSDL language

Design/editing of BS structures using the BSDL language

  • Design/description of the target board using several chips

Design/description of the target board using several chips

Applet on Boundary Scan

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A multi-layer research and training platform for system-on-chip testing

An applet targeted An applet targeted at binding all the at binding all the applets and the applets and the Turbo Tester Turbo Tester

Design for Design for Testability Testability Applet on Applet on Basics of Test Basics of Test & Diagnostics & Diagnostics Applet on Applet on RTL Design RTL Design and Test and Test Applet on Applet on Boundary Scan Boundary Scan Standard Standard

Schematic Schematic & DD Editor & DD Editor

AGM, DWG AGM, DWG AGM, GIF AGM, GIF AGM AGM AGM, AGM, GIF GIF

Main functions of the applet are: Main functions of the applet are:

  • gate

gate-

  • level schematic editor

level schematic editor

  • SSBDD editor

SSBDD editor

  • schematic

schematic ↔ ↔ SSBDD on SSBDD on-

  • the

the-

  • fly

fly converter converter

  • different format reader/converter

different format reader/converter

Schematic and DD editor

It is still a work in progress!

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A multi-layer research and training platform for system-on-chip testing

Example of a lab work scenario

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A multi-layer research and training platform for system-on-chip testing

Conclusions & Discussion

The main features of the platform:

  • Research engine + training software
  • Layered structure
  • HW and SW components
  • Remote access
  • Distance learning and e-learning
  • Computer-aided teaching
  • Freeware
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A multi-layer research and training platform for system-on-chip testing

Our Tools on the Web

The Turbo Tester home page

http://www.pld.ttu.ee/tt/

The Turbo Tester web-server page

http://www.pld.ttu.ee/webtt/

DefSim web-server page

http://www.defsim.com

Java applets home page

http://www.pld.ttu.ee/applets/