Scheduling complex streaming applications on the Cell processor - - PowerPoint PPT Presentation

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Scheduling complex streaming applications on the Cell processor

Mathias Jacquelin, joint work with Matthieu Gallet and Loris Marchal

INRIA ROMA project-team LIP (ENS-Lyon, CNRS, INRIA) ´ Ecole Normale Sup´ erieure de Lyon, France

Workshop on Multithreaded Architectures and Applications, Atlanta, April 23, 2010.

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Outline

Introduction Steady-state scheduling CELL Platform and Application Modeling Mapping the Application Practical Steady-State on CELL Preprocessing of the schedule State machine of the framework Experimental results Conclusion and Future works

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Motivation

◮ Multicore architectures: new opportunity to test the

scheduling strategies designed in the ROMA team.

◮ Our trademark: efficient scheduling on heterogeneous

platforms

◮ Most multicore architecture are homogeneous, regular

◮ Need for tailored algorithms (linear algebra,. . . )

◮ Emerging heterogeneous multicore:

◮ Dedicated processing units on GPUs ◮ Mixed system: processor + accelerator

◮ This study: steady-state scheduling on CELL (bounded

heterogeneity) to demonstrate the usefulness of complex (static) scheduling techniques

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Motivation

◮ Multicore architectures: new opportunity to test the

scheduling strategies designed in the ROMA team.

◮ Our trademark: efficient scheduling on heterogeneous

platforms

◮ Most multicore architecture are homogeneous, regular

◮ Need for tailored algorithms (linear algebra,. . . )

◮ Emerging heterogeneous multicore:

◮ Dedicated processing units on GPUs ◮ Mixed system: processor + accelerator

◮ This study: steady-state scheduling on CELL (bounded

heterogeneity) to demonstrate the usefulness of complex (static) scheduling techniques

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Motivation

◮ Multicore architectures: new opportunity to test the

scheduling strategies designed in the ROMA team.

◮ Our trademark: efficient scheduling on heterogeneous

platforms

◮ Most multicore architecture are homogeneous, regular

◮ Need for tailored algorithms (linear algebra,. . . )

◮ Emerging heterogeneous multicore:

◮ Dedicated processing units on GPUs ◮ Mixed system: processor + accelerator

◮ This study: steady-state scheduling on CELL (bounded

heterogeneity) to demonstrate the usefulness of complex (static) scheduling techniques

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Introduction: Steady-state Scheduling

Rationale:

◮ A pipelined application:

◮ Simple chain ◮ More complex application

(Directed Acyclic Graph)

◮ Objective: optimize the throughput

• f the application

(number of input files treated per seconds)

◮ Today: simple case where each

task has to be mapped on one single resource

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Introduction: Steady-state Scheduling

Rationale:

◮ A pipelined application:

◮ Simple chain ◮ More complex application

(Directed Acyclic Graph)

◮ Objective: optimize the throughput

• f the application

(number of input files treated per seconds)

◮ Today: simple case where each

task has to be mapped on one single resource

T1 T2 T3

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Introduction: Steady-state Scheduling

Rationale:

◮ A pipelined application:

◮ Simple chain ◮ More complex application

(Directed Acyclic Graph)

◮ Objective: optimize the throughput

• f the application

(number of input files treated per seconds)

◮ Today: simple case where each

task has to be mapped on one single resource

T1 T2 T3 T4 T5 T6 T7 T8 T9

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Introduction: Steady-state Scheduling

Rationale:

◮ A pipelined application:

◮ Simple chain ◮ More complex application

(Directed Acyclic Graph)

◮ Objective: optimize the throughput

• f the application

(number of input files treated per seconds)

◮ Today: simple case where each

task has to be mapped on one single resource

T1 T2 T3 T4 T5 T6 T7 T8 T9

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Introduction: Steady-state Scheduling

Rationale:

◮ A pipelined application:

◮ Simple chain ◮ More complex application

(Directed Acyclic Graph)

◮ Objective: optimize the throughput

• f the application

(number of input files treated per seconds)

◮ Today: simple case where each

task has to be mapped on one single resource

P2 P1 P3 P4

T5 T6 T7 T8 T9 T1 T2 T3 T4

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

EIB PPE0 SPE3 SPE2 SPE6 SPE7 SPE1 SPE0 SPE4 MEMORY SPE5

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

EIB SPE5 SPE3 SPE2 SPE6 SPE7 SPE1 SPE0 SPE4 PPE0 MEMORY

◮ 1 PPE core

◮ VMX unit ◮ L1, L2 cache ◮ 2 way SMT

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

EIB SPE4 SPE5 SPE2 SPE6 SPE7 SPE1 MEMORY SPE3 PPE0 SPE0

◮ 8 SPEs

◮ 128-bit SIMD instruction set ◮ Local store 256KB ◮ Dedicated Asynchronous DMA engine

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

EIB SPE5 SPE3 SPE2 SPE6 SPE7 SPE1 SPE0 SPE4 PPE0 MEMORY

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

EIB PPE0 SPE3 SPE2 SPE6 SPE7 SPE1 SPE0 SPE4 MEMORY SPE5

◮ Element Interconnect Bus (EIB)

◮ 200 GB/s bandwidth

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CELL brief introduction

◮ Multicore heterogeneous processor ◮ Accelerator extension to Power architecture

EIB PPE0 SPE4 SPE2 SPE6 SPE7 SPE1 SPE0 SPE5 MEMORY SPE3

◮ 25 GB/s bandwidth

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Outline

Introduction Steady-state scheduling CELL Platform and Application Modeling Mapping the Application Practical Steady-State on CELL Preprocessing of the schedule State machine of the framework Experimental results Conclusion and Future works

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Platform modeling

Simple CELL modeling:

◮ 1 PPE and 8 SPE: 9 processing elements P1, . . . , P9, with

unrelated speed,

◮ Each processing element access the communication bus with a

(bidirectional) bandwidth b = (25GB/s) ,

◮ The bus is able to route all concurrent communications

without contention (in a first step),

◮ Due to the limited size of the DMA stack on each SPE:

◮ Each SPE can perform at most 16 simultaneous DMA

• perations,

◮ The PPE can perform at most 8 simultaneous DMA

• perations to/from a given SPE.

◮ Linear cost communication model:

a data of size S is sent/received in time S/b

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Application modeling

Application is described by a directed acyclic graph:

◮ Tasks T1, . . . , Tn ◮ Processing time of task Tk on Pi is

ti(k),

◮ If there is a dependency Tk → Tl,

datak,l is the size of the file produced by Tk and needed by Tl,

T1 T2 T3 T4 T5 T6 T7 T8 T9

◮ If Tk is an input task, it reads readk bytes from main memory, ◮ If Tk is an output task, it writes writek bytes to main memory,

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Application modeling

Application is described by a directed acyclic graph:

◮ Tasks T1, . . . , Tn ◮ Processing time of task Tk on Pi is

ti(k),

◮ If there is a dependency Tk → Tl,

datak,l is the size of the file produced by Tk and needed by Tl,

T1 T2 T3 T4 T5 T6 T7 T8 T9

◮ If Tk is an input task, it reads readk bytes from main memory, ◮ If Tk is an output task, it writes writek bytes to main memory,

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Application modeling

Application is described by a directed acyclic graph:

◮ Tasks T1, . . . , Tn ◮ Processing time of task Tk on Pi is

ti(k),

◮ If there is a dependency Tk → Tl,

datak,l is the size of the file produced by Tk and needed by Tl,

T1 T2 T3 T4 T5 T6 T7 T8 T9

◮ If Tk is an input task, it reads readk bytes from main memory, ◮ If Tk is an output task, it writes writek bytes to main memory,

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Target application: any DAG

◮ Today, we will focus on three random task graphs:

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Target application: any DAG

◮ Today, we will focus on three random task graphs:

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Target application: any DAG

◮ Today, we will focus on three random task graphs:

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Target application: any DAG

◮ Today, we will focus on three random task graphs:

And a simple chain graph (50 tasks)

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Outline

Introduction Steady-state scheduling CELL Platform and Application Modeling Mapping the Application Practical Steady-State on CELL Preprocessing of the schedule State machine of the framework Experimental results Conclusion and Future works

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How to compute an optimal mapping

◮ Ojective: maximize throughput ρ ◮ Method: write a linear program gathering constraints on the

mapping

◮ Binary variables: αk i =

• 1

if Tk is mapped on Pi

• therwise

◮ Other useful binary variables: βk,l i,j = 1 iff file Tk → Tl is

transfered from Pi to Pj

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Constraints 1/2

On the application structure:

◮ Each task is mapped on a processor:

∀Tk

• i

αk

i = 1 ◮ Given a dependency Tk → Tl, the processor computing Tl

must receive the corresponding file: ∀(k, l) ∈ E, ∀Pj,

• i

βk,l

i,j ≥ αl j ◮ Given a dependency Tk → Tl, only the processor computing

Tk can send the corresponding file: ∀(k, l) ∈ E, ∀Pi,

• j

βk,l

i,j ≤ αk i

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Constraints 2/2

On the achievable throughput ρ = 1/T:

◮ On a given processor, all tasks must be completed within T:

∀Pi,

• k

αk

i × ti(k) ≤ T ◮ All incoming communications must be completed within T:

∀Pj, 1 b

k

αk

j × readk +

• k,l
• i

βk,l

i,j × datak,l

• ≤ T

◮ All outgoing communications must be completed within T:

∀Pi, 1 b

k

αk

i × writek +

• k,l
• i

βk,l

i,j × datak,l

• ≤ T

+ constraints on the number of incoming/outgoing communications to respect the DMA requirements + constraints on the available memory on SPE

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Optimal mapping computation

◮ Linear program with the objective of minimizing T ◮ Integer (binary) variables: Mixed Integer Programming ◮ NP-complete problem ◮ Efficient solvers exist with short running time

◮ for small-size problems ◮ or when an approximate solution is searched

◮ We use CPLEX, and look for an approximate solution (5% of

the optimal throughput is good enough)

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Outline

Introduction Steady-state scheduling CELL Platform and Application Modeling Mapping the Application Practical Steady-State on CELL Preprocessing of the schedule State machine of the framework Experimental results Conclusion and Future works

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

◮ min periodl = maxm∈precl(min periodm) + peekl + 2 ◮ min buffi,l = min periodl − min periodi

min periodk min periodl = maxm∈precl(min periodm) + peekl + 2 min buffj,l min buffi,l =min periodl − min periodi min periodj peekj peekk peeki peekl min buffi,k min buffi,j min periodi min buffk,l

Tl Ti Tk Tj

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

min buffi,j = 3 min buffj,l = 6 min periodl = 9 min buffi,l = 9 min buffk,l = 4 peeki = 0 min periodi = 0 peekj = 1 min periodj = 3 min periodk = 5 peekk = 3 peekl = 2 min buffi,k = 5

Tl Ti Tk Tj

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peekk = 3 peekl = 2 min buffi,k = 5 min buffi,j = 3 min periodl = 9 min buffi,l = 9 min buffj,l = 6 peeki = 0 min buffk,l = 4 min periodi = 0 min periodj = 3 peekj = 1 min periodk = 5

Ti Tk Tj Tl

period = 0

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

min buffj,l = 6 min buffi,j = 3 min buffi,k = 5 peekl = 2 peekk = 3 min periodj = 3 min periodi = 0 peeki = 0 min periodk = 5 min buffi,l = 9 min buffk,l = 4 peekj = 1 min periodl = 9

Tk Tl Tj Ti

period = 1

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peeki = 0 min buffk,l = 4 min buffj,l = 6 min buffi,j = 3 min buffi,k = 5 peekl = 2 peekk = 3 peekj = 1 min periodk = 5 min periodj = 3 min buffi,l = 9 min periodl = 9 min periodi = 0

Tl Tj Tk Ti

period = 2

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peekk = 3 min periodk = 5 peekj = 1 min periodj = 3 min periodi = 0 peeki = 0 min buffk,l = 4 min periodl = 9 min buffi,l = 9 min buffj,l = 6 min buffi,j = 3 min buffi,k = 5 peekl = 2

Tl Tj Tk Ti

period = 3

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peekk = 3 min periodk = 5 peekj = 1 min periodj = 3 min periodi = 0 peeki = 0 min buffk,l = 4 min periodl = 9 min buffi,l = 9 min buffj,l = 6 min buffi,j = 3 min buffi,k = 5 peekl = 2

Tl Tj Tk Ti

period = 4

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peekk = 3 min periodk = 5 peekj = 1 min periodj = 3 min periodi = 0 peeki = 0 min buffk,l = 4 min periodl = 9 min buffi,l = 9 min buffj,l = 6 min buffi,j = 3 min buffi,k = 5 peekl = 2

Tl Tj Tk Ti

period = 5

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peekk = 3 min periodk = 5 peekj = 1 min periodj = 3 min periodi = 0 peeki = 0 min buffk,l = 4 min periodl = 9 min buffi,l = 9 min buffj,l = 6 min buffi,j = 3 min buffi,k = 5 peekl = 2

Tl Tj Tk Ti

period = 6

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peekj = 1 min periodi = 0 min buffj,l = 6 peekk = 3 min buffi,j = 3 min periodk = 5 min periodj = 3 peeki = 0 min buffk,l = 4 min buffi,k = 5 peekl = 2 min periodl = 9 min buffi,l = 9

Tk Ti Tj Tl

period = 7

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

peeki = 0 peekj = 1 min periodk = 5 peekk = 3 peekl = 2 min buffi,k = 5 min buffi,j = 3 min buffj,l = 6 min periodl = 9 min buffi,l = 9 min periodi = 0 min buffk,l = 4 min periodj = 3

Ti Tk Tj Tl

period = 8

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Preprocessing of the schedule

Main Objective: Compute minimal starting period and buffer sizes.

min buffi,l = 9 min buffk,l = 4 peeki = 0 min periodi = 0 min periodj = 3 peekj = 1 min periodk = 5 peekl = 2 peekk = 3 min buffi,k = 5 min buffi,j = 3 min buffj,l = 6 min periodl = 9

Tj Tl Ti Tk

period = 9

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State machine of the framework

Two main phases: Computation and Communication

Select a Task Wait Resources Process Task Signal new Data

Computation Phase

Communicate

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State machine of the framework

Two main phases: Computation and Communication

Select a Task Wait Resources Communicate Signal new Data

Computation Phase

Process Task

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State machine of the framework

Two main phases: Computation and Communication

Communicate Wait Resources Process Task Signal new Data

Computation Phase

Communicate Select a Task

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State machine of the framework

Two main phases: Computation and Communication

Select a Task Wait Resources Communicate Signal new Data

Computation Phase

Process Task

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State machine of the framework

Two main phases: Computation and Communication

Select a Task Wait Resources Communicate Signal new Data

Computation Phase

Process Task

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State machine of the framework

Two main phases: Computation and Communication

No No more comm. No

Get Data Watch DMA Check input buffers Check input data

Communication Phase

Compute For each inbound comm.

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State machine of the framework

Two main phases: Computation and Communication

No No more comm. No

Check input data Watch DMA Check input buffers Get Data

Communication Phase

For each inbound comm. Compute

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State machine of the framework

Two main phases: Computation and Communication

No No more comm. No

Check input data Watch DMA Check input buffers Get Data

Communication Phase

For each inbound comm. Compute

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State machine of the framework

Two main phases: Computation and Communication

No No more comm. No

Check input data Watch DMA Check input buffers Get Data

Communication Phase

For each inbound comm. Compute

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State machine of the framework

Two main phases: Computation and Communication

No No more comm. No

Check input data Watch DMA Check input buffers Get Data

Communication Phase

For each inbound comm. Compute

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State machine of the framework

Two main phases: Computation and Communication

No No more comm. No

Check input data Watch DMA Check input buffers Get Data

Communication Phase

For each inbound comm. Compute

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Communication between processors

PK PL T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

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Communication between processors

Signal Data(i) PL T (i)

2

T (i+1)

1

T (i)

1

PK T (i−1)

2

mfc putb for SPEs’ outbound communications. spe mfcio getb for PPEs’ outbound communications to SPEs. memcpy for PPEs’ outbound communications to main memory.

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Communication between processors

cannot be overwritten Input buffers are available to store data Output buffer containing i

Signal Data(i) PL T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

PK

mfc putb for SPEs’ outbound communications. spe mfcio getb for PPEs’ outbound communications to SPEs. memcpy for PPEs’ outbound communications to main memory.

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Communication between processors

Get Data(i)

cannot be overwritten Input buffers are available to store data Output buffer containing i

Signal Data(i) T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

PK PL

mfc get for SPEs’ inbound communications. spe mfcio put for PPEs’ inbound communications from SPEs. memcpy for PPEs’ inbound communications from main memory.

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Communication between processors

Get Data(i)

cannot be overwritten Input buffers are available to store data Output buffer containing i

Signal Data(i) T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

PK PL

mfc get for SPEs’ inbound communications. spe mfcio put for PPEs’ inbound communications from SPEs. memcpy for PPEs’ inbound communications from main memory.

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Communication between processors

Transfer Done(i) Get Data(i)

Output buffer containing i cannot be overwritten Input buffers are available to store data

Signal Data(i) PL T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

PK

mfc putb for SPEs’ acknowledgements. spe mfcio getb for PPEs’ acknowledgements to SPEs. Self acknowledgement of PPEs’ transfers from main memory.

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Communication between processors

Output buffer containing i can now be overwritten

Transfer Done(i) Get Data(i)

Input buffers are available to store data Output buffer containing i cannot be overwritten

Signal Data(i) PL T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

PK

mfc putb for SPEs’ acknowledgements. spe mfcio getb for PPEs’ acknowledgements to SPEs. Self acknowledgement of PPEs’ transfers from main memory.

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Communication between processors

Signal Data(i + 1)

can now be overwritten Output buffer containing i

Transfer Done(i) Get Data(i)

Input buffers are available to store data Output buffer containing i cannot be overwritten

Signal Data(i) T (i−1)

2

T (i)

2

T (i+1)

1

T (i)

1

PK PL

mfc putb for SPEs’ acknowledgements. spe mfcio getb for PPEs’ acknowledgements to SPEs. Self acknowledgement of PPEs’ transfers from main memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Experimental setup

◮ Linear-Programming: 5% from optimal to reduce compute

time

◮ GreedyMem: Simple greedy heuristics balancing memory

footprint across PEs.

◮ Tasks are processed in topological order. ◮ Valid SPE with the least loaded memory is selected.

◮ GreedyCpu: Simple greedy heuristics balancing compute

load across PEs.

◮ Tasks are processed in topological order. ◮ Least loaded SPE is selected, provided that it has enough free

memory.

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Reaching steady state

Graph 1

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 Number of instances 5 10 15 20 25 30 35 40 Throughput (instances / seconds) Theoretical throughput Experimental throughput

95% of the theoretical throughput is achieved after 1000 periods

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Experimental results

Graph 1

Speed-up for 5000 instances 1 2 3 4 5 6 7 8 Number of SPEs 1 1.5 2 GreedyCpu GreedyMem Linear Programming

Results are obtained over 5000 periods, 2x speedup using 8 SPEs.

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Experimental results

Graph 2

Speed-up for 5000 instances 1 2 3 4 5 6 7 8 Number of SPEs 1 1.5 2 GreedyCpu GreedyMem Linear Programming

Results are obtained over 5000 periods, 2x speedup using 8 SPEs.

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Experimental results

Graph 3: 50 tasks deep chain graph

Speed-up for 5000 instances 1 2 3 4 5 6 7 8 Number of SPEs 1 1.5 2 2.5 3 GreedyCpu GreedyMem Linear Programming

Results are obtained over 5000 periods, 3x speedup using 8 SPEs.

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Experimental results

We let the communication to computation ratio of each graph vary

Speed-up for 10000 instances 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 Communication to computation ratio 1 1.5 2 2.5 3 3.5 4 Random graph 2 Random graph 3 Random graph 1

Results are obtained over 10000 periods. The heavier communication are, the harder it is to achieve theoretical throughput... ... but increasing the number of periods helps a lot.

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Outline

Introduction Steady-state scheduling CELL Platform and Application Modeling Mapping the Application Practical Steady-State on CELL Preprocessing of the schedule State machine of the framework Experimental results Conclusion and Future works

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Feedback on our approach

◮ We designed a realistic and yet tractable model of the Cell

processor.

◮ Our framework allowed us to test our scheduling strategy, and

to compare it to simpler heuristic strategies.

◮ We have shown that :

◮ 95% of the throughput predicted by the linear program, ◮ Good and scalable speedup when using up to 8 SPEs, ◮ Clearly outperforms simple heuristics

Scheduling a complex application on a heterogeneous multicore processor is a challenging task Scheduling tools can help to achieve good performance.

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Feedback on Cell programming

◮ Multilevel heterogeneity:

◮ 32 bits SPEs vs 64 bits PPE architectures ◮ Different communication mechanism and constraints

◮ Non trivial initialization phase

◮ Varying data structure sizes (32/64bits) ◮ Runtime memory allocation

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On-going and Future work

◮ Better communication modeling

◮ Is linear cost model relevant ? ◮ Contention on concurrent DMA operations ?

◮ Larger platforms

◮ Using multiple CELL processors ◮ CELL + other type of processing units ? ◮ Work on communication modeling

◮ Design scheduling heuristics

◮ MIP is costly