ROAD: Routablility Analysis & Diagnosis Based on SAT Techniques - - PowerPoint PPT Presentation
ROAD: Routablility Analysis & Diagnosis Based on SAT Techniques ISPD 2019 UCSD VLSI LAB Dongwon Park , Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin, Chung-Kuan Cheng 1 P HYSICAL D ESIGN GETTING H ARDER P HYSICAL D ESIGN GETTING H ARDER
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Given Pin-Layout ILP: Optimal but 1048s (~18min) !
Placement Gate Netlist Routable?
Power Rail Pin 16 15 14 11 4 6 2 8 9 Pin 12 13 1 5 3 7 10 18 20 22 23 17
Via3-4 M1-2 M2-3 M3-4
21 19
SAT : Not Optimized but 2s !!!!! SAT Method → Quick “go/no-go” Decision
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Routability Analysis Flow
Logic Simplification
Testcase (i.e., Switchbox) Generation
Inputs
Switchboxes
ILP Inputfiles Reduced SAT Inputfiles
Our Proposed Framework
Logic Minimizer
Espresso [26]
ILP Patterns
per ILP Formula
Results of Routability Analysis by ILP by SAT
Solvers
ILP-to-SAT Conversion SAT Solver Portfolio
Plingling / Glucose-syrup / many-Glucose
ILP Solver
CPLEX [27] SAT Inputfiles
SAT-Friendly ILP Formulation
ILP Result: Routing Feasibility, Wirelength, Metal Cost, etc. SAT Result: Routing Feasibility, SAT Solution if Satisfiable
[27] IBM ILOG CPLEX, http://www.ilog.com/products/cplex/. [28] plingeling, Multi-Threading SAT Solver, http://fmv.jku.at/lingeling/.
Fast and Precise Routability Analysis w
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▪ Conditional Design Rule (D) ▪ Layout Structure Map (L)
Commodity Flow Conservation (CFC)
Exclusiveness Use
Edge Assignment (EA) Metal Segment (MS) Geometry Variable (GV)
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▪ CASE I) Vertex ≠ source, sink : 0 or 2 edges uses ▪ CASE II) Vertex = source, sink : Exactly-One (EO) Commodity Flow Constraint.
1) Only one incoming/outgoing pair is allowable for all commodities. 2) This commodity don’t use this vertex.
(𝑤) (𝑤) (𝑤) (𝑤)
𝑔
𝑛 𝑜(𝑤)
𝑔
𝑛 𝑜(𝑤, )
𝑔
𝑛 𝑜(𝑤, )
(𝑤) (𝑤) (𝑤) (𝑤) (𝑤) (𝑤)
𝑔
𝑛 𝑜(𝑤)
(𝑤) (𝑤) (𝑤) (𝑤) (𝑤)
𝑔
𝑛 𝑜(𝑤)
𝑔
𝑛 𝑜(𝑤, )
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▪ CASE I. Vertex ≠ source, sink : At-Most-One (AMO) Net Constraint ▪ CASE II. Vertex = source, sink : Exactly-One (EO) Edge Constraint
2) No Flow 1) Only one net can use a certain edge
(𝑤)
𝑣 𝑣
(𝑤) (𝑤) 𝑓𝑤,
𝑜
𝑓𝑤,𝑣
𝑜
𝑓𝑤,𝑣
𝑜
(𝑤) (𝑤) (𝑤) (𝑤) (𝑤) (𝑤)
(𝑤) (𝑤) (𝑤) (𝑤) (𝑤) 𝑓𝑤,
𝑜
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▪ Commander Encoding Variable of EO constraint of edge indicators
𝑛 𝑜(𝑤, 𝑣) → 𝑓𝑤,𝑣 𝑜
Logical Imply. : edge is used by n net if m commodity of n net use this edge → It requires for multi-commodity flow
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▪ End-of-Line indicator of each vertex for geometric conditional design rule.
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▪ A metal segment must cover at least three vertices (AMO Constraint)
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▪ The minimum distance between tips must be larger than 2 Manhattan distance (AMO Constraint)
No Violation Violation Violation
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▪ The distance between two vias should be larger sqrt(2) Euclidean Distance (AMO constraint)
𝑤𝑉𝐺 𝑤 𝑤𝑉𝐺𝑆
𝑁𝑗 𝑁𝑗+1 𝑁𝑗+2
𝑤𝑉 𝑤𝑉𝐶 𝑤𝑉𝑆 𝑤𝑉𝐶𝑆 𝑤𝑉𝐺𝑀 𝑤𝑉𝑀 𝑤𝑉𝐶𝑀 𝑤𝐺𝑀 𝑤𝑀 𝑤𝐶𝑀 𝑤𝐺 𝑤 𝑤𝐺𝑆 𝑤𝑆 𝑤𝐶𝑆 𝑤𝐶
𝑁𝑗 𝑁𝑗+1 𝑁𝑗+2
𝑤𝐺𝐺 𝑤𝐶𝐶
Violation No Violation
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▪ Conjunction of each subsets
▪ L : Layout Structure Map → the geometry information of the switch box
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▪ Exact Location of Conflict → Fast Trouble-shooting for Designer ▪ Exact Conflict Relation → Guideline for Design Rule Manager
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Decision (DLS)
(Decision with Longest-Path Search)
Propagation (PTA/PFA)
(Propagation with True/False Assignment)
Routability Analysis Using SAT Formulation Conflict Information
(Conflict Geometry / Design Rule)
Conflict?
Yes No
MUS Extraction
(Minimal Unsatisfiable Subset)
Initial Propagation
(Geometric Information of Switch-Box)
BCP Iteration Ub Up Us MUS PIG DAG : H(U,D)
Node : U (variable) Edge : D (clause)
Unroutable Layout Conflict Region Clause Minimization
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https://en.wikipedia.org/wiki/Unit_propagation
▪ Directed Acyclic Graph which Nodes are Variables, Edges are Clauses. ▪ The implication relation between variable assignment from constraint clause
a = 1 c = 1 d = 1
PIG of the propagation ¬ ∪ 𝑑 ¬𝑑 ∪ 𝑒 Clause set: ∪ 𝑐 , ¬ ∪ 𝑑, ¬𝑑 ∪ 𝑒, 1𝑡𝑢 𝐶𝐷𝑄, = 1 → 𝑑, ¬𝑑 ∪ 𝑒 𝑠𝑓𝑛 𝑗𝑜 2𝑜𝑒 𝐶𝐷𝑄, 𝑑 = 1 → 𝑒 𝑠𝑓𝑛 𝑗𝑜
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2 3 12 9 7 1 4 13 5 10 8 11 6
{3 10}, {13 19}, {9 12}, {4 17}, {8 14}, {0 16}, {5, 15}, {11 21}
Power Rail
Estimated Conflict Region
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
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▪ Via Position / Direction of Element are determined at DLS phase
2 3 12 9 7 1 4 13 5 10 8 11 6 2 3 12 9 7 1 4 13 5 10 8 11 6
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
Conflict @ 2nd 2 3 12 9 7 1 4 13 5 10 8 11 6 Conflict @ 1st Conflict @ 4th Blocked via (M1 ↔ M2)
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2 3 12 9 7 1 4 13 5 10 8 11 6
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
Blocked via (M1 ↔ M2) Blocked via (M2 ↔ M3) Assigned via (M1 ↔ M2)
𝑛 3,10,1 ,(3,10,2) = 1 𝑊𝑆 𝑛(4,9,1)(4,9,2) = 0 𝑛(4,10,1)(4,10,2) = 0 𝑓 4,9,1 ,(4,9,2)
9
= 0 𝑁𝑇 𝑔
9(4,9,1)(4,9,2) = 0
𝐹𝐵 𝑓 4,10,1 ,(4,10,2)
9
= 0 𝑁𝑇 𝑔
9(4,10,1)(4,10,2) = 0
𝐹𝐵 𝑛(3,10,2)(3,10,3) = 0 𝑓 3,10,2 ,(3,10,3)
6
= 0 𝑁𝑇 𝑔
6(3,10,2)(3,10,3) = 0
𝐹𝐵 𝑊𝑆 𝑊𝑆 (𝑇𝑢 𝑑𝑙𝑓𝑒) 𝐵𝑡𝑡𝑗𝑜𝑓𝑒 𝐺 𝑚𝑡𝑓
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▪ Via-to-via spacing / Stacked – Via / Vias in same pin / element with direction against PTA
𝑤
𝑁𝑗 𝑁𝑗+1 𝑁𝑗+2
𝑤𝑉 𝑤𝐺𝑀 𝑤𝑀 𝑤𝐶𝑀 𝑤𝐺 𝑤 𝑤𝐺𝑆 𝑤𝑆 𝑤𝐶𝑆 𝑤𝐶
𝑁𝑗 𝑁𝑗+1 𝑁𝑗+2
𝑤𝐶𝐶
Blocked via
𝑤
𝑁1 𝑁2
𝑤𝐺 𝑤𝐶 𝑤
𝑁1 𝑁2
𝑤𝑉 𝑤𝑉𝑀 𝑤𝑉𝑆
Blocked in-layer element
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2 3 12 9 7 1 4 13 5 10 8 11 6
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
Blocked via (M1 ↔ M2) Blocked via (M2 ↔ M3) Assigned via (M1 ↔ M2) Blocked in-layer element
𝑔
9( 𝑗𝑜11)(4,10,1) = 0
𝑔
9( 𝑗𝑜11)(4,9,1) = 0
𝑔
9(4,9,1)(4,10,1) = 0
𝐷𝐺𝐷
𝑔
9( 𝑗𝑜11)(4,8,1) = 1
𝐷𝐺𝐷
𝑔
9(4,8,1)(4,9,1) = 0
𝐷𝐺𝐷 𝐷𝐺𝐷 𝐷𝐺𝐷
𝑔
9(4,8,1)(4,8,2) = 1
𝐷𝐺𝐷 𝐷𝐺𝐷 𝑓 4,8,1 ,(4,8,2)
9
= 1 𝐹𝐵 𝑛(4,8,1)(4,8,2) = 1 𝑁𝑇 𝑛(4,8,2)(4,8,3) = 0 𝑊𝑆 𝑓 4,8,2 ,(4,8,3)
9
= 0
𝑔
9(4,8,2)(4,8,3) = 0
𝑁𝑇 𝐹𝐵 𝐶𝑚𝑝𝑑𝑙𝑓𝑒 𝑈𝑠𝑣𝑓 𝐺 𝑚𝑡𝑓 𝑛 3,10,2 ,(4,10,2) = 0 𝐻𝑊 𝑛(4,10,2)(5,10,2) = 0 𝑓 4,10,2 ,(5,10,2)
8
= 0 𝑁𝑇
𝑔
8(4,10,2)(5,10,2) = 0
𝐹𝐵 𝑓 5,10,2 ,(6,10,2)
8
= 0
𝑔
9(4,10,1)(4,10,2) = 0
𝐹𝐵 𝑓 3,10,2 ,(4,10,2)
6
= 0 𝑁𝑇
𝑔
6(3,10,2)(4,10,2) = 0
𝐹𝐵 𝐻𝑊 𝑆,(3,10,2) = 1 𝑀,(4,10,2) = 0 𝐹𝑃𝑀 𝐻𝑊 𝑀,(5,10,2) = 0 𝐹𝑃𝑀 𝑛(5,10,2)(6,10,2) = 0 𝐻𝑊 𝐻𝑊 𝑁𝑇
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2 3 12 9 7 1 4 13 5 10 8 11 6
Blocked via (M1 ↔ M2) CONFLICT Information
𝑔
7( 𝑗𝑜0)(7,8,1) = 0
𝑔
7( 𝑗𝑜0)(7,9,1) = 0
𝑔
7( 𝑗𝑜0)(7,10,1) = 1
𝐷𝐺𝐷 𝐷𝐺𝐷 𝑔
7( 𝑗𝑜0)(7,10,1) = 0
𝐶𝑚𝑝𝑑𝑙𝑓𝑒 𝑈𝑠𝑣𝑓 𝐺 𝑚𝑡𝑓
1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8
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▪ Conflict Pin-shape (CP) : Pin-Accessibility Problem!
▪ Simple-CP : Intrinsic Pattern in given Pin-layout ▪ Propagated-CP : Simple-CP appears after some propagations
▪ Routing Congestion
▪ The lack of routing resources such as #Track and #Layer
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2 3 12 9 7 1 4 13 5 10 8 11 6
Simple Intrinsic CP Pattern 3 – 3 – n – 3 – 3
{4 17}, {8 14}, {0 16}, {5, 15}, {11 21}
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→ Why designer don’t change Pin-shape?
11 3 5 7 13 4 2 1 8 6 10 12 9
Propagated CP Pattern 3 – 3 – 3
11 3 5 7 13 4 2 1 8 6 10 12 9
{6 20}, {3 16}, {7 17}, {5 11}, {9 19}, {1 18} 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11
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{1 4}, {7 19}, {0 17}, {10 18}
`
11 2 3 1 6 5 10 8 9 7 4
`
11 2 3 1 6 5 10 8 9 7 4
(a)
` 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 1 1 1 1 2 1 3 1 4
All tracks are occupied / blocked !!
11 2 3 1 6 5 10 8 9 7 4
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▪ MUS Extraction Time + Decision & Propagation Time ▪ Diagnosis Performance (Complexity and Execution Time) depends on the root causes of routing failure
▪ CP pattern case is less than 30 seconds on average to get the result. ▪ Routing Congestion Case is relatively longer than the CP pattern cases.
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Routability Analysis with Conditional Design Rules”. SLIP 2018
“ RODE: Efficient Routability Diagnosis and Estimation Framework Based on SAT Techniques”. ISPD 2019
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2 2 2 2 2 1 1 1
M1 in G M2 in G M3 in G M4 in G
PIN #1
1
Power Rail H-Track Outer-Pin Connection V-Track Grid
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▪ SAT (Boolean Satisfiability)
→ Find a variable assignment to make propositional logic formula evaluates to 1(True) (Satisfiable) , or prove that no such assignment exists (Unsatisfiable) →Usually, Product of Sum (i.e. CNF) is normal representation for SAT formula
𝐷𝑚 𝑣𝑡𝑓
X Y F(x,y) 1 1 1 1 1 1
Sum of Product (DNF)
Product of Sum (CNF) Truth Table Equivalent Representations