RFNoC: Evolving SDR Toolkits to the FPGA platgorm Martjn Braun - - PowerPoint PPT Presentation

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RFNoC: Evolving SDR Toolkits to the FPGA platgorm Martjn Braun - - PowerPoint PPT Presentation

Dec 30, 2022 498 likes •836 views

RFNoC: Evolving SDR Toolkits to the FPGA platgorm Martjn Braun 31.1.2016 USRP: A White Box? Simple OFDM Transmituer Development: FPGA handles All the interesting parts processed on GPP DUC, CORDIC, etc. transparently Entjre

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SLIDE 1

RFNoC™: Evolving SDR Toolkits to the FPGA platgorm

Martjn Braun 31.1.2016

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SLIDE 2
  • Simple OFDM Transmituer Development:
  • Entjre Hardware stack is treated like a

reprogrammable ASIC, Features are used as-is

USRP: A White Box?

All the interesting parts processed on GPP FPGA handles DUC, CORDIC, etc. transparently

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SLIDE 3
  • Everything USRP is available online (code,

schematjcs)

  • Contains big and expensive FPGA!

Open the Box!

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SLIDE 4

FPGAs: Hard to use… slow to develop

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SLIDE 5
  • Know Thy Audience!
  • FPGA development is not a requirement of a

communications engineering curriculum

  • Math is hard too

Domain vs FPGA Experts

Theory Experts FPGA Experts

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SLIDE 6
  • Simple in Theory: 200 MHz real-tjme, Welch's

Algorithm

Example: Wideband Spectral Analysis

Highly parallelizable operations, basic math => Ideal to shift to FPGA Transport: Overloaded FPGA: Underutilized

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SLIDE 7
  • Heterogeneous Processing
  • Support composable and modular designs using

GPP, FPGA, & beyond

  • Maintain ease of use
  • Tight integratjon with GNU Radio

Goal

FPGA Processing GPP Processing

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SLIDE 8
  • Heterogeneous Processing
  • Support composable and modular designs using

GPP, FPGA, & beyond

  • Maintain ease of use
  • Tight integratjon with popular SDR frameworks

Goal

FPGA Processing GPP Processing

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SLIDE 9
  • Make FPGA acceleratjon easier

(especially on USRPs)

  • Sofuware API + FPGA infrastructure
  • Handles FPGA – Host communicatjon / datafmow
  • Provides user simple sofuware and HDL interfaces
  • Scalable design for massive distributed processing
  • Fully supported in GNU Radio

RFNoC: RF Network on Chip

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SLIDE 10

RFNoC Architecture

User Applicatjon – GNU Radio

Crossbar Ingress Egress Interface USRP Hardware Driver Radio Core

HOST PC USRP FPGA

Computatjon Engine Computatjon Engine

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SLIDE 11

RFNoC Architecture

User Applicatjon – GNU Radio

Crossbar Ingress Egress Interface USRP Hardware Driver Radio Core

HOST PC USRP FPGA

Computatjon Engine Computatjon Engine

  • Example: Plottjng frequency spectrum
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SLIDE 12

RFNoC Architecture

User Applicatjon – GNU Radio

Crossbar Ingress Egress Interface USRP Hardware Driver Radio Core

HOST PC USRP FPGA

Computatjon Engine Computatjon Engine

  • Radio block in GNU Radio represents the Radio

Core RFNoC block in FPGA

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SLIDE 13

RFNoC Architecture

User Applicatjon – GNU Radio

Crossbar Ingress Egress Interface USRP Hardware Driver Radio Core

HOST PC USRP FPGA

Computatjon Engine Computatjon Engine

  • RFNoC provides the

communicatjon infrastructure

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SLIDE 14

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Application – GNU Radio

Radio Core

HOST PC USRP FPGA

RFNoC Block RFNoC Block

  • RFNoC provides space for user logic called

Computatjon Engines

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SLIDE 15

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Application – GNU Radio

Radio Core

HOST PC USRP FPGA

RFNoC Block RFNoC Block

  • RFNoC provides space for user logic called

Computatjon Engines

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SLIDE 16

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Application – GNU Radio

Radio Core

HOST PC USRP FPGA

RFNoC Block RFNoC Block

  • Implement FFT as a

Computatjon Engine in FPGA

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SLIDE 17

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Applicatjon – GNU Radio

Radio Core

HOST PC USRP FPGA

FFT RFNoC Block

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SLIDE 18

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Applicatjon – GNU Radio

Radio Core

HOST PC USRP FPGA

FFT Dogecoin Mining

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SLIDE 19

Computatjon Engine

Crossbar

FFT

FIFO FIFO Packetjzer Xilinx FFT IP

Radio Core

Depacketjzer FIFO FIFO RX DSP

RX Sample Data To Host PC

TX DSP Depacketjzer Packetjzer AXI-Stream

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SLIDE 20
  • FIFO to FIFO, packetjzatjon, fmow control
  • Provided by RFNoC infrastructure

Computatjon Engine

Crossbar

FFT

FIFO FIFO Packetjzer Xilinx FFT IP

Radio Core

Depacketjzer FIFO FIFO RX DSP AXI-Stream

RX Sample Data To Host PC

TX DSP Depacketjzer Packetjzer

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SLIDE 21
  • User interfaces to RFNoC via AXI-Stream
  • Industry standard (ARM), easy to use
  • Large library of existjng IP cores

Computatjon Engine

Crossbar

FFT

FIFO FIFO Packetjzer Xilinx FFT IP

Radio Core

Depacketjzer FIFO FIFO RX DSP

To Host PC

TX DSP Depacketjzer Packetjzer

RX Sample Data

AXI-Stream

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SLIDE 22
  • User writes their own HDL or drops in IP
  • Multjple AXI-Streams, Control / Status registers

Computatjon Engine

Crossbar

FFT

FIFO FIFO Packetjzer Xilinx FFT IP

Radio Core

Depacketjzer FIFO FIFO RX DSP

To Host PC

TX DSP Depacketjzer Packetjzer

RX Sample Data

AXI-Stream

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SLIDE 23

Computatjon Engine

Crossbar

FFT

FIFO FIFO Packetjzer Xilinx FFT IP

Radio Core

Depacketjzer FIFO FIFO RX DSP AXI-Stream

RX Sample Data To Host PC

TX DSP Depacketjzer Packetjzer

  • Each block is in their own clock domain
  • Improve block throughput, tjming
  • Interface to Crossbar has clock crossing FIFOs
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SLIDE 24
  • Many computatjon engines
  • Not limited to one crossbar, one device
  • Scales across devices for massive distributed

processing

Many Types of CEs

Crossbar Radio Core FFT FIR Demodulator Crypto Core Compression Decompression Sofu Processor MicroBlaze

To Other RFNoC Capable Device

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SLIDE 25
  • Low latency protocol processing in FPGA

Many Types of Blocks

Crossbar Radio Core FFT FIR Demodulator Crypto Core Compression Decompression Sofu Processor MicroBlaze

To Other RFNoC Capable Device

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SLIDE 26

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Applicatjon – GNU Radio

Radio Core

HOST PC USRP FPGA

FFT Twituer Parser

  • Transparent protocol conversion
  • Multjple standards PCI-E, 10 GigE, AXI
  • Could be wire through -- forwarding to another crossbar
  • Parallel interfaces (example: X300 has 2 x 10 GigE)
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SLIDE 27

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Applicatjon – GNU Radio

Radio Core

HOST PC USRP FPGA

FFT TrumpScript Executor

  • Sofuware API to:
  • Confjgure USRP hardware & RFNoC FPGA infrastructure
  • Provide user sample data (r/w bufgers) & control (r/w regs) interfaces
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SLIDE 28

USRP Hardware Driver Crossbar Ingress Egress Interface

RFNoC Architecture

User Applicatjon – GNU Radio

Radio Core

HOST PC USRP FPGA

FFT Computatjon Engine

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SLIDE 29

DEMO

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SLIDE 30

RFNoC Stack

GRC Bindings (XML) GNU Radio Integration Block Code (Python / C++) Block Declaration (XML / NocScript) Block Controller (C++) UHD Integration UHD Integration FPGA Integration Verilog / VHDL / CoreGen / IP

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SLIDE 31

RFNoC Stack (Simple)

GRC Bindings (XML) GNU Radio Integration Default Block Block Declaration (XML / NocScript) Default Block Controller UHD Integration UHD Integration FPGA Integration Verilog / VHDL / CoreGen / IP

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SLIDE 32

RFNoC Stack (Even Simpler)

Your Application here! Block Declaration (XML / NocScript) Default Block Controller UHD Integration UHD Integration FPGA Integration Verilog / VHDL / CoreGen / IP

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SLIDE 33
  • Simple architecture for heterogeneous data fmow

processing

  • Several interestjng blocks already exist
  • Integrated with GNU Radio
  • Portable between all third generatjon USRPs
  • X3x0, E310, and products soon to come
  • Completely open source (within Xilinx toolchains)
  • Available on github!
  • github.com/EtuusResearch/uhd/wiki/RFNoC:-Gettjng-

Started

Summary