RFNoC: Evolving SDR Toolkits to the FPGA platgorm Martjn Braun - PowerPoint PPT Presentation

RFNoC™: Evolving SDR Toolkits to the FPGA platgorm Martjn Braun 31.1.2016

USRP: A White Box?  Simple OFDM Transmituer Development: FPGA handles All the interesting parts processed on GPP DUC, CORDIC, etc. transparently  Entjre Hardware stack is treated like a reprogrammable ASIC, Features are used as-is

Open the Box!  Everything USRP is available online (code, schematjcs)  Contains big and expensive FPGA!

FPGAs: Hard to use… slow to develop

Domain vs FPGA Experts  Know Thy Audience!  FPGA development is not a requirement of a communications engineering curriculum  Math is hard too Theory FPGA Experts Experts

Example: Wideband Spectral Analysis  Simple in Theory: 200 MHz real-tjme, Welch's Algorithm FPGA: Highly parallelizable operations, basic math Underutilized => Ideal to shift to FPGA Transport: Overloaded

Goal  Heterogeneous Processing  Support composable and modular designs using GPP, FPGA, & beyond  Maintain ease of use  Tight integratjon with GNU Radio FPGA GPP Processing Processing

Goal  Heterogeneous Processing  Support composable and modular designs using GPP, FPGA, & beyond  Maintain ease of use  Tight integratjon with popular SDR frameworks FPGA GPP Processing Processing

RFNoC: RF Network on Chip  Make FPGA acceleratjon easier (especially on USRPs)  Sofuware API + FPGA infrastructure  Handles FPGA – Host communicatjon / datafmow  Provides user simple sofuware and HDL interfaces  Scalable design for massive distributed processing  Fully supported in GNU Radio

RFNoC Architecture User Applicatjon – GNU Radio HOST PC USRP Hardware Driver Ingress Egress Interface USRP FPGA Crossbar Computatjon Computatjon Radio Core Engine Engine

RFNoC Architecture User Applicatjon – GNU Radio HOST PC  USRP Hardware Driver Example: Plottjng frequency spectrum Ingress Egress Interface USRP FPGA Crossbar Computatjon Computatjon Radio Core Engine Engine

RFNoC Architecture User Applicatjon – GNU Radio HOST PC  USRP Hardware Driver Radio block in GNU Radio represents the Radio Core RFNoC block in FPGA Ingress Egress Interface USRP FPGA Crossbar Computatjon Computatjon Radio Core Engine Engine

RFNoC Architecture User Applicatjon – GNU Radio  RFNoC provides the communicatjon infrastructure HOST PC USRP Hardware Driver Ingress Egress Interface USRP FPGA Crossbar Computatjon Computatjon Radio Core Engine Engine

RFNoC Architecture User Application – GNU Radio HOST PC USRP Hardware Driver  RFNoC provides space for user logic called Computatjon Engines Ingress Egress Interface USRP FPGA Crossbar Radio Core RFNoC Block RFNoC Block

RFNoC Architecture User Application – GNU Radio HOST PC USRP Hardware Driver  RFNoC provides space for user logic called Computatjon Engines Ingress Egress Interface USRP FPGA Crossbar Radio Core RFNoC Block RFNoC Block

RFNoC Architecture User Application – GNU Radio HOST PC  USRP Hardware Driver Implement FFT as a Computatjon Engine Ingress Egress Interface USRP FPGA in FPGA Crossbar Radio Core RFNoC Block RFNoC Block

RFNoC Architecture User Applicatjon – GNU Radio HOST PC USRP Hardware Driver Ingress Egress Interface USRP FPGA Crossbar RFNoC Block Radio Core FFT

RFNoC Architecture User Applicatjon – GNU Radio HOST PC USRP Hardware Driver Ingress Egress Interface USRP FPGA Crossbar Radio Core FFT Dogecoin Mining

Computatjon Engine To Host PC Crossbar Radio Core FFT Depacketjzer Packetjzer Depacketjzer Packetjzer FIFO FIFO FIFO FIFO AXI-Stream TX DSP RX DSP Xilinx FFT IP RX Sample Data

Computatjon Engine To Host PC Crossbar Radio Core FFT Depacketjzer Packetjzer Depacketjzer Packetjzer FIFO FIFO FIFO FIFO AXI-Stream TX DSP RX DSP Xilinx FFT IP RX Sample Data  FIFO to FIFO, packetjzatjon, fmow control  Provided by RFNoC infrastructure

Computatjon Engine To Host PC Crossbar Radio Core FFT Depacketjzer Packetjzer Depacketjzer Packetjzer FIFO FIFO FIFO FIFO AXI-Stream TX DSP RX DSP Xilinx FFT IP RX Sample Data  User interfaces to RFNoC via AXI-Stream  Industry standard (ARM), easy to use  Large library of existjng IP cores

Computatjon Engine To Host PC Crossbar Radio Core FFT Depacketjzer Packetjzer Depacketjzer Packetjzer FIFO FIFO FIFO FIFO AXI-Stream TX DSP RX DSP Xilinx FFT IP RX Sample Data  User writes their own HDL or drops in IP  Multjple AXI-Streams, Control / Status registers

Computatjon Engine To Host PC Crossbar Radio Core FFT Depacketjzer Packetjzer Depacketjzer Packetjzer FIFO FIFO FIFO FIFO AXI-Stream TX DSP RX DSP Xilinx FFT IP RX Sample Data  Each block is in their own clock domain  Improve block throughput, tjming  Interface to Crossbar has clock crossing FIFOs

Many Types of CEs To Other RFNoC Capable Device Crossbar Radio Core FFT FIR Demodulator Compression Sofu Processor Crypto Core Decompression MicroBlaze  Many computatjon engines  Not limited to one crossbar, one device  Scales across devices for massive distributed processing

Many Types of Blocks To Other RFNoC Capable Device Crossbar Radio Core FFT FIR Demodulator Compression Sofu Processor Crypto Core Decompression MicroBlaze  Low latency protocol processing in FPGA

RFNoC Architecture User Applicatjon – GNU Radio  Transparent protocol conversion  Multjple standards PCI-E, 10 GigE, AXI HOST PC  Could be wire through -- forwarding to another crossbar  USRP Hardware Driver Parallel interfaces (example: X300 has 2 x 10 GigE) Ingress Egress Interface USRP FPGA Crossbar Radio Core FFT Twituer Parser

RFNoC Architecture User Applicatjon – GNU Radio HOST PC USRP Hardware Driver  Ingress Egress Interface USRP FPGA Sofuware API to:  Confjgure USRP hardware & RFNoC FPGA infrastructure Crossbar  Provide user sample data (r/w bufgers) & control (r/w regs) interfaces TrumpScript Radio Core FFT Executor

RFNoC Architecture User Applicatjon – GNU Radio HOST PC USRP Hardware Driver Ingress Egress Interface USRP FPGA Crossbar Computatjon Radio Core FFT Engine

DEMO

RFNoC Stack GNU Radio Integration GRC Bindings (XML) Block Code (Python / C++) UHD Integration UHD Integration Block Declaration (XML / NocScript) Block Controller (C++) FPGA Integration Verilog / VHDL / CoreGen / IP

RFNoC Stack (Simple) GNU Radio Integration GRC Bindings (XML) Default Block UHD Integration UHD Integration Block Declaration (XML / NocScript) Default Block Controller FPGA Integration Verilog / VHDL / CoreGen / IP

RFNoC Stack (Even Simpler) Your Application here! UHD Integration UHD Integration Block Declaration (XML / NocScript) Default Block Controller FPGA Integration Verilog / VHDL / CoreGen / IP

Summary  Simple architecture for heterogeneous data fmow processing  Several interestjng blocks already exist  Integrated with GNU Radio  Portable between all third generatjon USRPs  X3x0, E310, and products soon to come  Completely open source (within Xilinx toolchains)  Available on github!  github.com/EtuusResearch/uhd/wiki/RFNoC:-Gettjng- Started