Real-time Harris and Stephen implementation on Smart camera Merwan - - PowerPoint PPT Presentation
Workshop on Architecture of Smart Camera Real-time Harris and Stephen implementation on Smart camera Merwan BIREM Franois BERRY 5-6 April 2012 Clermont-Ferrand, FRANCE 1 Summary 1 - Feature Extraction, 2 - Harris & Stephen detector,
Workshop on Architecture of Smart Camera
5-6 April 2012 Clermont-Ferrand, FRANCE
Merwan BIREM François BERRY
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1 - Feature Extraction, 2 - Harris & Stephen detector, 3 – The hardware implementation,
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3 – The hardware implementation, 4 – The results of the implementation, 5 – The DreamCAM,
1 - Feature Extraction :
is used to describe the combination of feature detector, and a feature descriptor. Harris & Stephen algorithm Feature detector A simple descriptor, which gives for each interest point an intensity patch from the Feature descriptor
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an intensity patch from the image (its neighbors).
2 - Harris & Stephen detector (1988) : 1/2
Currently, most of the computer vision algorithm use interest point of type Harris & Stephen as input.
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Because : It is based on simple principal, Gives acceptable results
2 - Harris & Stephen detector (1988) : 2/2
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3 -The hardware implementation : 1/4
Communication Board (Firewire)
Sensing boards
SeeMOS: FPGA SeeMOS: FPGA-
based smart cam
FPGA board
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FPGA
Global memory Private memories (SRAM-10ns) 1MB 1MB 1MB 1MB 1MB Inertial Navigation Set: 3 accelerometers 3 gyrometers 5 Data/@ /@ CMOS Imager 4 Mpixels
3 -The hardware implementation : 2/4
SeeMOS SeeMOS Synoptic Synoptic
FPGA
memory
ADC
Conversion control Windows of Interest control Data/@ IEEE1394
Softcore
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3 -The hardware implementation : 3/4
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light in data frame out
3 -The hardware implementation : 3/4
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light in data frame out
3 -The hardware implementation : 3/4
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light in data frame out
3 -The hardware implementation : 3/4
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light in data frame out
3 -The hardware implementation : 3/4
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light in data frame out
3 -The hardware implementation : 4/4
The data frame :
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The maximal frequency = 22.52MHz, The FPGA resources used :
From the compilation report : (for image 256x256 pixels)
4 –The results of the implementation : 1/2 The FPGA resources used :
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Logic Elements 11'327 / 57'120 20% Memory Bits 1'066'376 / 5'215'104 20% DSP-block 33 / 44 23%
4 –The results of the implementation : 2/2
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5 –The DreamCAM Anatomy :
Memory board 6 x 1Mb Sensors board (GPS, inertial,…)
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IBIS5 1. 3Mpixels Image sensor Power board Cyclone III, FPGA
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