Ratchet Intermittent Computation without Hardware Support or - - PowerPoint PPT Presentation

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Ratchet Intermittent Computation without Hardware Support or - - PowerPoint PPT Presentation

Jul 24, 2023 508 likes •802 views

Ratchet Intermittent Computation without Hardware Support or Programmer Intervention University of Michigan Ma>hew Hicks Joel Van Der Woude MIT/LL Sandia 12/5/16 jvdw@umich.edu 1 12/5/16 jvdw@umich.edu 2 Batteries are bulky and

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Ratchet Intermittent Computation without Hardware Support or

Programmer Intervention

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Joel Van Der Woude Sandia Ma>hew Hicks MIT/LL University of Michigan

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SLIDE 2

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Batteries are bulky and inconvenient

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Energy harvesting

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Hardware monitoring vs. 
 programmer insight

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  • r
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Goals of Ratchet

  • Burden the compiler not the programmer
  • Without hardware to measure voltage
  • Ensure forward progress under frequent

power failures (~100ms)

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Checkpointing

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  • Save volatile state

to non-volatile memory

  • After a power fail

– restart – restore – continue

Time Progress

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Initial Correct At Fail Error a x y y 42 b y 42 42 42

Re-execution causes incorrectness

mem[a] = mem[b] mem[b] = 42 … return a

Write a(er Read (WAR)

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Initial Correct At Fail a x y y b y 42 42 Initial Correct a x y b y 42 Initial mem[a] x mem[b] y

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SLIDE 9

What is idempotence?

  • Re-execution generates semantically

correct result

  • A section of code that does not overwrite/

update inputs

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Initial Correct At Fail Error a x y y y b y 42 42 42

Idempotence enabling re-execution

mem[a] = mem[b] mem[b] = 42 … return a

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Initial Correct At Fail a x y y b y 42 42 Initial Correct a x y b y 42 Initial a x b y

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Ratchet system overview

11 12/5/16 jvdw@umich.edu Ratchet Ratchet .o file .c file Frontend Instruction Selection & Register Allocation Finalize Idempotence Analysis Insert Checkpoints Fix-up Combine Redundant Checkpoints Emit Minimum Checkpoint IR IR ASM ASM Function Entry

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Idempotence analysis

12 12/5/16 jvdw@umich.edu Ratchet Ratchet .o file .c file Frontend Instruction Selection & Register Allocation Finalize Idempotence Analysis Insert Checkpoints Fix-up Combine Redundant Checkpoints Emit Minimum Checkpoint IR IR ASM ASM Function Entry

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mem[a] = mem[b] mem[b] = 42 … return a

Identifying WARs

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Insert checkpoints

14 12/5/16 jvdw@umich.edu Ratchet Ratchet .o file .c file Frontend Instruction Selection & Register Allocation Finalize Idempotence Analysis Insert Checkpoints Fix-up Combine Redundant Checkpoints Emit Minimum Checkpoint IR IR ASM ASM Function Entry

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Seperating WARs with checkpoints

  • Weighted with

– Loop depth – # of WAR cut

15 mem[c] = 42 r0 = mem[a] r1 = mem[b] r3 = φ(r0,r2) mem[a] = r3+1 mem[c] = r1 mem[b] = r1+1 r2 = mem[c] r2 = mem[c] checkpoint() 12/5/16 jvdw@umich.edu checkpoint() mem[b] = r1+1

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Fix-up

16 12/5/16 jvdw@umich.edu Ratchet Ratchet .o file .c file Frontend Instruction Selection & Register Allocation Finalize Idempotence Analysis Insert Checkpoints Fix-up Combine Redundant Checkpoints Emit Minimum Checkpoint IR IR ASM ASM Function Entry

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The backend may create WARs

  • Stack Teardown
  • Register Spilling

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… return addr r0-r3 locals

SP

new addr new regs

12/5/16 jvdw@umich.edu

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Redundant checkpoints

18 12/5/16 jvdw@umich.edu Ratchet Ratchet .o file .c file Frontend Instruction Selection & Register Allocation Finalize Idempotence Analysis Insert Checkpoints Fix-up Combine Redundant Checkpoints Emit Minimum Checkpoint IR IR ASM ASM Function Entry

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Relocating checkpoints to combine

  • Redundant checkpoints

caused by…

– Optimizations – Scheduling Decisions – Register Spills

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r0 = mem[a] r1 = mem[b] r3 = r0+r1 r4 = r3+1 checkpoint() R5 = r3+r4 mem[a] = r3 checkpoint() mem[b] = r5 r0 = mem[a] r1 = mem[b] r3 = r0+r1 r4 = r3+1 checkpoint() r5 = r3+r4 mem[a] = r3 mem[b] = r5

jvdw@umich.edu

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Minimum checkpoint

20 12/5/16 jvdw@umich.edu Ratchet Ratchet .o file .c file Frontend Instruction Selection & Register Allocation Finalize Idempotence Analysis Insert Checkpoints Fix-up Combine Redundant Checkpoints Emit Minimum Checkpoint IR IR ASM ASM Function Entry

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Optimizing Ratchet

  • Ratchet

Unoptimized

  • RatchetFE

Function Entry

  • RatchetFE+RD

+Remove Duplicates

  • RatchetFE+RD+LR +Live Registers
  • Ideal

Single Checkpoint

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How we evaluated Ratchet

  • Simulator

– Cycle accurate – Random power failures – Dynamically track idempotence

– https://github.com/impedimentToProgress/thumbulator

  • Benchmarks

– MIBench – newlib

– https://github.com/impedimentToProgress/MiBench2

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Conclusion

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Questions?

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