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PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive Computer Architecture Research Derek Lockhart, Berkin Ilbeyi, Christopher Batten Computer Systems Laboratory School of Electrical and Computer Engineering Cornell University

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PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive Computer Architecture Research

Derek Lockhart, Berkin Ilbeyi, Christopher Batten

Computer Systems Laboratory School of Electrical and Computer Engineering Cornell University 42nd Int’l Symp. on Computer Architecture, June 2015

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Overview

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Presentation Pydgin Intro Hands-On GCD Instr Presentation PyMTL Intro Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Typical Research Methodologies: Application-Level

Register-Transfer Level Circuits Devices Instruction Set Arch. Programming Language Algorithm Microarchitecture Technology Application Operating System Gate Level

I General Approach

. Use real machines . Use real machines with dynamic

instrumentation (e.g., Pin)

. Use fast instruction set simulators or

emulators (e.g., SimIt-ARM, QEMU)

I Benefits

. Fast execution enables experimenting

with large, realistic applications

I Challenges

. Difficult to explore applications for

emerging architectures which do not exist yet

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Presentation Pydgin Intro Hands-On GCD Instr Presentation PyMTL Intro Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Typical Research Methodologies: Architecture-Level

Register-Transfer Level Circuits Devices Instruction Set Arch. Programming Language Algorithm Microarchitecture Technology Application Operating System Gate Level

I General Approach

. Use standard benchmark suite (e.g.,

Splash2, PARSEC, Rodina)

. Modify standard cycle-level C/C++

simulator (e.g., SESC, Simics, gem5)

. Use standard high-level physical modeling

tool (e.g., CACTI, Wattch, Orion, McPAT)

I Benefits

. More accurate than ISA simulation . Faster and more flexible design-space

exploration than lower-level models

I Challenges

. Experimenting with large, realistic apps . Physical modeling of radically new arch

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Presentation Pydgin Intro Hands-On GCD Instr Presentation PyMTL Intro Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Typical Research Methodologies: VLSI-Level

Register-Transfer Level Circuits Devices Instruction Set Arch. Programming Language Algorithm Microarchitecture Technology Application Operating System Gate Level

I General Approach

. Possibly start with open-source IP (e.g.,

FabScalar, OpenRISC/SPARC, NetMaker)

. Write small microbenchmarks or

embedded applications

. Implement SystemVerilog/Verilog/VHDL

RTL (or Bluespec GAA) model of design

. Use standard commercial ASIC CAD tools

to estimate cycle time, area, energy

I Benefits

. More accurate physical characterization . Increases credibility of design

I Challenges

. Only small apps possible due to slow sims . Cumbersome design-space exploration

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Vertically-Integrated Modeling Environment

Register-Transfer Level Circuits Devices Instruction Set Arch. Programming Language Algorithm Microarchitecture Technology Application Operating System Gate Level App Arch VLSI

I Unified package with integrated

applications, test programs, cross compilers, proxy kernels, full OS kernels, ISA emulators, microarchitectural models, RTL models, ASIC/FPGA CAD scripts, and unit tests

I Support for rapid/iterative

design-space exploration across abstraction layers especially for emerging applications and radically new architectures

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Highly Productive Modeling Environment

Change Simulator Configuration Time Sim Modify Simulator Slightly Sim Modify Simulator Significantly Sim + Write Emerging Apps + Implement RTL Models Sim Highly Productive Modeling Env Sim

I Choose language at the

application, architecture, and VLSI level to emphasize productivity over performance

I Possibly use a single language

at all abstraction levels

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Previous Vertically Integrated Methodology

Cross Compiler Native Compiler C++ ISA Sim Cross Binary Native Binary C++ Application Kernel

Software Toolflow

C++ Microarch Sim Verilog RTL Gate-Level Model Verilog RTL Simulator Verilog GL Simulator Switching Activity Power Analysis

Hardware Toolflow

Layout Synthesis Place&Route

Results

Area & Cycle Time Cycle Count Energy Software and hardware toolflows are driven by a combination of Makefiles and Autoconf

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Python-Based Vertically Integrated Methodology

Cross Compiler Native Compiler C++ ISA Sim Cross Binary Native Binary C++ Application Kernel

Software Toolflow

C++ Microarch Sim Verilog RTL Gate-Level Model Verilog RTL Simulator Verilog GL Simulator Switching Activity Power Analysis

Hardware Toolflow

Layout Synthesis Place&Route

Results

Area & Cycle Time Cycle Count Energy Software and hardware toolflows are driven by a combination of Makefiles and Autoconf Pydgin ISA Sim PyMTL FL & CL Sim PyMTL RTL Sim PyMTL RTL

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Why Python?

I Python is well regarded as a highly productive

language with lightweight, pseudocode-like syntax

I Python supports modern language features to

enable rapid, agile development (dynamic typing, reflection, metaprogramming)

I Python has a large and active developer and support community I Python includes extensive standard and third-party libraries I Python enables embedded domain-specific languages I Python facilitates engaging application-level researchers I Python includes built-in support for integrating with C/C++ I Python performance is improving with advanced JIT compilation

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What is PyMTL?

A!Python!EDSL!for!concurrentNstructural!hardware!modeling!
A!Python!API!for!analyzing!models!described!in!the!PyMTL!EDSL!!
A!Python!tool!for!simulaBng!PyMTL!FL,!CL,!and!RTL!models!
A!Python!tool!for!translaBng!PyMTL!RTL!models!into!Verilog!
A!Python!tesBng!framework!for!model!validaBon!

! !

API! SimulaBon! Tool! TranslaBon! Tool! Model!EDSL! TesBng!Framework!

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What is PyMTL for and not (currently) for?

I PyMTL is for ...

. Taking an accelerator design from concept to implementation . Construction of highly-parameterizable RTL chip generators . Rapid design, testing, and exploration of hardware mechanisms . Quickly prototyping models and interfacing them with GEM5 . Interfacing models with imported Verilog

I PyMTL is not (currently) for ...

. Python high-level synthesis . Many-core simulations with hundreds of cores . Full-system simulation with real OS support . Users needing a complex OOO processor model “out of the box” . Users needing an ARM/x86 processor model “out of the box” . Users needing a mature modeling framework that will not change

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What is Pydgin?

Pydgin is a Python-based framework for productively generating very fast instruction-set simulators

InstrucBon!Set! Interpreter!in!C! with!DBT! Architectural! DescripBon! Language!

Pydgin

I Flexible, productive, pseudocode-like ADL syntax I ADL embedded in a popular, general-purpose language I Tracing-JIT generator applies across many different ISAs I Leverages advancements from dynamic-language JIT research I Capable of simulating RISC instruction sets at 100’s of MIPS

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Presentation Pydgin Intro Hands-On GCD Instr Presentation PyMTL Intro Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

What is Pydgin for and not (currently) for?

I Pydgin is for ...

. Building your own very fast instruction set simulators . Experimenting with emerging research instruction sets . Easily instrumenting an instruction set simulator for early analysis

I Pydgin is not (currently) for ...

. Multi-core simulations (planned for the near future) . Full-system simulation . Users needing an ARMv8/x86 simulator “out of the box” . Users needing a mature modeling framework that will not change

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PyMTL/Pydgin in Practice

I PyMTL/Pydgin in Research

. PyMTL CL modeling used in recent XLOOPS accelerator project . PyMTL/Pydgin modeling used in current HLS accelerator work . PyMTL/Pydgin modeling used in current data-parallel accelerator work . Pydgin used in porting PBBS to our PARC instruction set

I PyMTL/Pydgin in Teaching

. Graduate-Level Complex Digital ASIC Design Course . Undergraduate-Level Computer Architecture Course

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PyMTL

PyMTL: A Unified Framework for Vertically Integrated Computer Architecture Research [ MICRO 2014 ]

https://github.com/cornell-brg/pymtl

Pydgin

Pydgin: Generating Fast Instruction Set Simulators from Simple Architecture Descriptions with Meta-Tracing JIT Compilers [ ISPASS 2015 ]

https://github.com/cornell-brg/pydgin

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PyMTL/Pydgin Project Sponsors

Funding partially provided by the National Science Foundation through NSF CAREER Award #1149464 Funding partially provided by the Defense Advanced Research Projects Agency through a DARPA Young Faculty Award

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PyMTL/Pydgin Tutorial Organizers

Derek Lockhart

I Nth-Year Ph.D. Candidate, ECE, Cornell University I Graduating this summer and heading to Google Platforms I Research Interests: Hardware design methodologies,

computer architecture, VLSI design

I Lead researcher/developer for PyMTL framework I Co-Lead researcher/developer for Pydgin framework

Berkin Ilbeyi

I 3nd-Year Ph.D. Candidate, ECE, Cornell University I Research Interests: Computer architecture, just-in-time

compilation, novel hardware/software interfaces

I First “real” user of PyMTL framework for XLOOPS project I Co-Lead researcher/developer for Pydgin framework

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PyMTL/Pydgin Tutorial Schedule

8:30am – 8:50am Virtual Machine Installation and Setup 8:50am – 9:00am Presentation: PyMTL/Pydgin Tutorial Overview 9:00am – 9:10am Presentation: Introduction to Pydgin 9:10am – 10:00am Hands-On: Adding a GCD Instruction using Pydgin 10:00am – 10:10am Presentation: Introduction to PyMTL 10:10am – 11:00am Hands-On: PyMTL Basics with Max/RegIncr 11:00am – 11:30am Coffee Break 11:30am – 11:40am Presentation: Multi-Level Modeling with PyMTL 11:40am – 12:30pm Hands-On: FL, CL, RTL Modeling of a GCD Unit

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