PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive - PowerPoint PPT Presentation

PyMTL and Pydgin Tutorial Python Frameworks for Highly Productive Computer Architecture Research Derek Lockhart, Berkin Ilbeyi, Christopher Batten Computer Systems Laboratory School of Electrical and Computer Engineering Cornell University 42nd Int’l Symp. on Computer Architecture, June 2015

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Typical Research Methodologies: Application-Level I General Approach Application . Use real machines Algorithm . Use real machines with dynamic Programming Language instrumentation (e.g., Pin) Operating System . Use fast instruction set simulators or Instruction Set Arch. emulators (e.g., SimIt-ARM, QEMU) Microarchitecture I Benefits Register-Transfer Level . Fast execution enables experimenting Gate Level with large, realistic applications Circuits I Challenges Devices . Difficult to explore applications for Technology emerging architectures which do not exist yet PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 2 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Typical Research Methodologies: Architecture-Level I General Approach Application . Use standard benchmark suite (e.g., Algorithm Splash2, PARSEC, Rodina) Programming Language . Modify standard cycle-level C/C++ Operating System simulator (e.g., SESC, Simics, gem5) Instruction Set Arch. . Use standard high-level physical modeling tool (e.g., CACTI, Wattch, Orion, McPAT) Microarchitecture Register-Transfer Level I Benefits Gate Level . More accurate than ISA simulation Circuits . Faster and more flexible design-space Devices exploration than lower-level models Technology I Challenges . Experimenting with large, realistic apps . Physical modeling of radically new arch PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 3 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Typical Research Methodologies: VLSI-Level I General Approach Application . Possibly start with open-source IP (e.g., Algorithm FabScalar, OpenRISC/SPARC, NetMaker) Programming Language . Write small microbenchmarks or Operating System embedded applications Instruction Set Arch. . Implement SystemVerilog/Verilog/VHDL RTL (or Bluespec GAA) model of design Microarchitecture . Use standard commercial ASIC CAD tools Register-Transfer Level to estimate cycle time, area, energy Gate Level I Benefits Circuits Devices . More accurate physical characterization Technology . Increases credibility of design I Challenges . Only small apps possible due to slow sims . Cumbersome design-space exploration PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 4 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Vertically-Integrated Modeling Environment I Unified package with integrated Application App applications, test programs, Algorithm cross compilers, proxy kernels, Programming Language full OS kernels, ISA emulators, Operating System microarchitectural models, RTL Instruction Set Arch. Arch models, ASIC/FPGA CAD Microarchitecture scripts, and unit tests Register-Transfer Level I Support for rapid/iterative Gate Level VLSI Circuits design-space exploration across Devices abstraction layers especially for emerging applications and Technology radically new architectures PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 5 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Highly Productive Modeling Environment Change Simulator I Choose language at the Sim Configuration application, architecture, and Time VLSI level to emphasize productivity over performance Modify Simulator Sim Slightly I Possibly use a single language at all abstraction levels Modify Simulator Sim Significantly + Write Emerging Apps Sim + Implement RTL Models Highly Productive Sim Modeling Env PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 6 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Previous Vertically Integrated Methodology Software Toolflow Hardware Toolflow Results C++ Application Kernel Verilog RTL Cycle Count Native Cross Verilog RTL Synthesis Area Compiler Compiler Simulator Place&Route & Cycle Time Native Binary Cross Binary Gate-Level Model Layout Verilog GL C++ C++ Simulator ISA Sim Microarch Sim Switching Activity Software and hardware toolflows are driven by a combination of Power Makefiles and Autoconf Energy Analysis PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 7 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Python-Based Vertically Integrated Methodology Software Toolflow Hardware Toolflow Results C++ Application Kernel PyMTL RTL Verilog RTL Cycle Count Native Cross Verilog RTL PyMTL Synthesis Area Compiler Compiler Simulator RTL Sim Place&Route & Cycle Time Native Binary Cross Binary Gate-Level Model Layout Verilog GL Pydgin C++ PyMTL C++ Simulator ISA Sim ISA Sim Microarch Sim FL & CL Sim Switching Activity Software and hardware toolflows are driven by a combination of Power Makefiles and Autoconf Energy Analysis PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 8 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit Why Python? I Python is well regarded as a highly productive language with lightweight, pseudocode-like syntax I Python supports modern language features to enable rapid, agile development (dynamic typing, reflection, metaprogramming) I Python has a large and active developer and support community I Python includes extensive standard and third-party libraries I Python enables embedded domain-specific languages I Python facilitates engaging application-level researchers I Python includes built-in support for integrating with C/C++ I Python performance is improving with advanced JIT compilation PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 9 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit What is PyMTL? ! • A!Python!EDSL!for!concurrentNstructural!hardware!modeling! • A!Python!API!for!analyzing!models!described!in!the!PyMTL!EDSL!! • A!Python!tool!for!simulaBng!PyMTL!FL,!CL,!and!RTL!models! • A!Python!tool!for!translaBng!PyMTL!RTL!models!into!Verilog! • A!Python!tesBng!framework!for!model!validaBon! ! TesBng!Framework! Model!EDSL! SimulaBon! ! Tool! API! TranslaBon! Tool! PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 10 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit What is PyMTL for and not (currently) for? I PyMTL is for ... . Taking an accelerator design from concept to implementation . Construction of highly-parameterizable RTL chip generators . Rapid design, testing, and exploration of hardware mechanisms . Quickly prototyping models and interfacing them with GEM5 . Interfacing models with imported Verilog I PyMTL is not (currently) for ... . Python high-level synthesis . Many-core simulations with hundreds of cores . Full-system simulation with real OS support . Users needing a complex OOO processor model “out of the box” . Users needing an ARM/x86 processor model “out of the box” . Users needing a mature modeling framework that will not change PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 11 / 125

⇣ Presentation Presentation Hands-On Presentation Hands-On Presentation Hands-On ⌘ Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit What is Pydgin? Pydgin is a Python-based framework for productively generating very fast instruction-set simulators Architectural! InstrucBon!Set! Pydgin DescripBon! Interpreter!in!C! Language! with!DBT! I Flexible, productive, pseudocode-like ADL syntax I ADL embedded in a popular, general-purpose language I Tracing-JIT generator applies across many different ISAs I Leverages advancements from dynamic-language JIT research I Capable of simulating RISC instruction sets at 100’s of MIPS PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research ISCA 2015 12 / 125