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May 29, 2023 •358 likes •1.31k views

PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' Computer'Architecture'Research' Derek'Lockhart,'Gary'Zibrat,'and'Christopher'Ba>en' Cornell'University' Computer'Systems'Laboratory' Outline( The'Computer'Architecture' PyMTL'

  1. PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' Computer'Architecture'Research' Derek'Lockhart,'Gary'Zibrat,'and'Christopher'Ba>en' Cornell'University' Computer'Systems'Laboratory'

  2. Outline( The'Computer'Architecture' PyMTL' Research'Methodology'Gap' The'PerformanceF SimJIT' ProducGvity'Gap' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 1'/'39' Computer'Architecture'Research'

  3. Trends(in(Computing(Systems( Energy'&'Power' Constrained' Credible'' Energy'and'Power' Analysis' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 2'/'39' Computer'Architecture'Research'

  4. Trends(in(Computing(Systems( Energy'&'Power' Extensive' Constrained' SpecializaGon' Credible'' ProducGve' Energy'and'Power' Design'Space'ExploraGon' Analysis' of'Specialized'Units' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 2'/'39' Computer'Architecture'Research'

  5. Trends(in(Computing(Systems( Energy'&'Power' Extensive' CrossFLayer' Constrained' SpecializaGon' OpGmizaGon' Credible'' ProducGve' EffecGve' Energy'and'Power' Design'Space'ExploraGon' Strategies'for' Analysis' of'Specialized'Units' VerGcally'Integrated' Design' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 2'/'39' Computer'Architecture'Research'

  6. Managing(Increasing(Design(Complexity( • AbstracGons' '' ' • Methodologies' '' ' • Pa>erns,'Languages,'Tools' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 3'/'39' Computer'Architecture'Research'

  7. Computer(Architecture(Research(Abstractions( • AbstracGons' '' ' • Methodologies' '' ' • Pa>erns,'Languages,'Tools' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 3'/'39' Computer'Architecture'Research'

  8. Computer(Architecture(Research(Abstractions( ApplicaGons' Algorithms' Compilers' InstrucGon'Set'Architecture' Microarchitecture' VLSI' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 4'/'39' Computer'Architecture'Research'

  9. Computer(Architecture(Research(Abstractions( ApplicaGons' Algorithms' Compilers' Industry' Academic' Development' Research' InstrucGon'Set'Architecture' ' ' Hundreds'of' A'Few'' Microarchitecture' Engineers' Researchers' VLSI' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 4'/'39' Computer'Architecture'Research'

  10. Computer(Architecture(Research(Abstractions( ApplicaGons' Algorithms' Compilers' Industry' Academic' Development' Research' InstrucGon'Set'Architecture' ' ' Hundreds'of' A'Few'' Microarchitecture' Engineers' Researchers' VLSI' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 4'/'39'' Computer'Architecture'Research'

  11. Computer(Architecture(Research(Methodologies( • AbstracGons' '' ' • Methodologies' '' ' • Pa>erns,'Languages,'Tools' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 5'/'39' Computer'Architecture'Research'

  12. Computer(Architecture(Research(Methodologies( ApplicaGons' Algorithms' Compilers' Cycle'Level' • Behavior' InstrucGon'Set'Architecture' • Timing' Microarchitecture' VLSI' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 6'/'39' Computer'Architecture'Research'

  13. Computer(Architecture(Research(Methodologies( ApplicaGons' Algorithms' Compilers' Cycle'Level' • Behavior' InstrucGon'Set'Architecture' • Timing' Microarchitecture' VLSI' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 6'/'39' Computer'Architecture'Research'

  14. Computer(Architecture(Research(Methodologies( ApplicaGons' FuncGonal'Level' • Behavior' Algorithms' Compilers' Cycle'Level' • Behavior' InstrucGon'Set'Architecture' • Timing' Microarchitecture' VLSI' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 6'/'39' Computer'Architecture'Research'

  15. Computer(Architecture(Research(Methodologies( ApplicaGons' FuncGonal'Level' • Behavior' Algorithms' Compilers' Cycle'Level' • Behavior' InstrucGon'Set'Architecture' • Timing' Microarchitecture' Register'Transfer'Level' VLSI' • Behavior' • Timing' • Physical'Resources' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 6'/'39' Computer'Architecture'Research'

  16. Computer(Architecture(Research(Methodologies( ApplicaGons' FuncGonal'Level' • Behavior' Algorithms' Compilers' Cycle'Level' • Behavior' InstrucGon'Set'Architecture' • Timing' Microarchitecture' Register'Transfer'Level' VLSI' • Behavior' • Timing' • Physical'Resources' Sea'of'Transistors' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 6'/'39' Computer'Architecture'Research'

  17. Computer(Architecture(Research(Methodologies( FuncGonal'Level' • Behavior' Cycle'Level' Modeling'Towards'Layout • Behavior' • Timing' Register'Transfer'Level' • Behavior' • Timing' • Physical'Resources' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 7'/'39' Computer'Architecture'Research'

  18. Computer(Architecture(Research(Methodologies( FuncGonal'Level' Greater'' Algorithm'and'ISA' Simula8on' Development' Speed' Cycle'Level' Modeling'Towards'Layout Design'Space' Explora8on' Register'Transfer'Level' Greater'' Model' Area/Energy/Timing'Valida8on' Detail' and' Prototype'Development' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 7'/'39' Computer'Architecture'Research'

  19. Computer(Architecture(Research(Frameworks( • AbstracGons' '' ' • Methodologies' '' ' • Pa>erns,'Languages,'Tools' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 8'/'100'' Computer'Architecture'Research'

  20. Computer(Architecture(Research(Frameworks( MATLAB/Python'Algorithm'or' FuncGonal'Level' C++'InstrucGon'Set'Simulator' Algorithm'and'ISA' Development' C++'Computer'Architecture'' Cycle'Level' SimulaGon'Framework' Design'Space' (ObjectFOriented)' Explora8on' Verilog'or'VHDL'Design'with' Register'Transfer'Level' EDA'Toolflow' Area/Energy/Timing'Valida8on' (ConcurrentFStructural)' and' Prototype'Development' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 9'/'100'' Computer'Architecture'Research'

  21. Computer(Architecture(Research(Frameworks( FuncGonal'Level' Different'languages,'' pa>erns,'and'tools! Algorithm'and'ISA' Development' Cycle'Level' The'Computer'Architecture' Design'Space' Research'Methodology'Gap Explora8on' Register'Transfer'Level' Area/Energy/Timing'Valida8on' and' Prototype'Development' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 9'/'100'' Computer'Architecture'Research'

  22. Great(Ideas(From(Prior(Work( • ConcurrentVStructural'Modeling ' Consistent'interfaces'across'abstracGons' (Liberty,'Cascade,'SystemC) ! ' ! PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 10'/'100'' Computer'Architecture'Research'

  23. Great(Ideas(From(Prior(Work( • ConcurrentVStructural'Modeling ' Consistent'interfaces'across'abstracGons' (Liberty,'Cascade,'SystemC) ! ' ! ' • Unified'Modeling'Languages' Unified'design'environment'for'FL,'CL,'RTL' (SystemC)' ' ' ' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 10'/'100'' Computer'Architecture'Research'

  24. Great(Ideas(From(Prior(Work( • ConcurrentVStructural'Modeling ' Consistent'interfaces'across'abstracGons' (Liberty,'Cascade,'SystemC) ! ' ! ' • Unified'Modeling'Languages' Unified'design'environment'for'FL,'CL,'RTL' (SystemC)' ' ' ' • Hardware'Genera8on'Languages' ProducGve'RTL'design'space'exploraGon' (Chisel,'Genesis2,'BlueSpec,'MyHDL)' ' ' ' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 10'/'100'' Computer'Architecture'Research'

  25. Great(Ideas(From(Prior(Work( • ConcurrentVStructural'Modeling ' Consistent'interfaces'across'abstracGons' (Liberty,'Cascade,'SystemC) ! ' ! ' • Unified'Modeling'Languages' Unified'design'environment'for'FL,'CL,'RTL' (SystemC)' ' ' ' • Hardware'Genera8on'Languages' ProducGve'RTL'design'space'exploraGon' (Chisel,'Genesis2,'BlueSpec,'MyHDL)' ' ' ' • HDLVIntegrated'Simula8on'Frameworks' ProducGve'RTL'validaGon'and'cosimulaGon' (Cascade) ! ' ' ' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 10'/'100'' Computer'Architecture'Research'

  26. Great(Ideas(From(Prior(Work( • ConcurrentVStructural'Modeling ' Consistent'interfaces'across'abstracGons' (Liberty,'Cascade,'SystemC) ! ' ! ' • Unified'Modeling'Languages' Unified'design'environment'for'FL,'CL,'RTL' (SystemC)' ' ' ' • Hardware'Genera8on'Languages' ProducGve'RTL'design'space'exploraGon' (Chisel,'Genesis2,'BlueSpec,'MyHDL)' ' ' ' • HDLVIntegrated'Simula8on'Frameworks' ProducGve'RTL'validaGon'and'cosimulaGon' (Cascade) ! ' ! ' • LatencyVInsensi8ve'Interfaces' Component'and'test'bench'reuse' (Liberty,'BlueSpec) ' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 10'/'100'' Computer'Architecture'Research'

  27. Outline( The'Computer'Architecture' PyMTL' Research'Methodology'Gap' The'PerformanceF SimJIT' ProducGvity'Gap' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 11'/'39' Computer'Architecture'Research'

  28. What(is(PyMTL?( • A'Python'DSEL'for'concurrentFstructural'hardware'modeling' Model'DSEL' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 12'/'39' Computer'Architecture'Research'

  29. What(is(PyMTL?( ' • A'Python'DSEL'for'concurrentFstructural'hardware'modeling' • A'Python'API'for'analyzing'models'described'in'the'PyMTL'DSEL' ' Model'DSEL' API' PyMTL:'A'Unified'Framework'for'Ver8cally'Integrated' 12'/'39' Computer'Architecture'Research'

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