PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine - - PowerPoint PPT Presentation

▶

Dec 05, 2022 257 likes •356 views

Presentation Presentation Presentation Hands-On Hands-On Presentation Hands-On Overview Pydgin Intro GCD Instr PyMTL Intro Max/RegIncr ML Modeling GCD Unit PyMTL/Pydgin Tutorial Schedule 8:30am 8:50am Virtual Machine

SLIDE 1

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

PyMTL/Pydgin Tutorial Schedule

8:30am – 8:50am Virtual Machine Installation and Setup 8:50am – 9:00am Presentation: PyMTL/Pydgin Tutorial Overview 9:00am – 9:10am Presentation: Introduction to Pydgin 9:10am – 10:00am Hands-On: Adding a GCD Instruction using Pydgin 10:00am – 10:10am Presentation: Introduction to PyMTL 10:10am – 11:00am Hands-On: PyMTL Basics with Max/RegIncr 11:00am – 11:30am Coffee Break 11:30am – 11:40am Presentation: Multi-Level Modeling with PyMTL 11:40am – 12:30pm Hands-On: FL, CL, RTL Modeling of a GCD Unit

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 51 / 125

SLIDE 2

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Computer Architecture Research Abstractions

Sea!of!Transistors! ApplicaBons! Algorithms! InstrucBon!Set!Architecture! Microarchitecture! VLSI! Compilers! Academic& Research& & A!Few!! Researchers! Industry& Development& & Hundreds!of! Engineers!

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 52 / 125

SLIDE 3

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Computer Architecture Research Methodologies

FuncBonal!Level! Cycle!Level! Register!Transfer!Level! Algorithm&and&ISA& Development& Design&Space& Explora>on& Area/Energy/Timing&Valida>on& and& Prototype&Development&

Modeling&Towards&Layout

Greater&& Simula>on& Speed& Greater&& Model& Detail&

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 53 / 125

SLIDE 4

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Computer Architecture Research Toolflows

FuncBonal!Level! Cycle!Level! Register!Transfer!Level! Algorithm&and&ISA& Development& Design&Space& Explora>on& Area/Energy/Timing&Valida>on& and& Prototype&Development&

Different!languages,!! paKerns,!and!tools! The&Computer&Architecture& Research&Methodology&Gap

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 54 / 125

SLIDE 5

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

Great Ideas From Prior Frameworks

ConcurrentUStructural&Modeling!

(Liberty,!Cascade,!SystemC)" "

Unified&Modeling&Languages&

(SystemC)! !

Hardware&Genera>on&Languages&

(Chisel,!Genesis2,!BlueSpec,!MyHDL)! !

HDLUIntegrated&Simula>on&Frameworks&

(Cascade)" "

LatencyUInsensi>ve&Interfaces&

(Liberty,!BlueSpec)&

Consistent!interfaces!across!abstracBons! ! ! Unified!design!environment!for!FL,!CL,!RTL! ! ! ProducBve!RTL!design!space!exploraBon! ! ! ProducBve!RTL!validaBon!and!cosimulaBon! ! ! Component!and!test!bench!reuse!

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 55 / 125

SLIDE 6

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

What is PyMTL?

!

A!Python!EDSL!for!concurrentNstructural!hardware!modeling!
A!Python!API!for!analyzing!models!described!in!the!PyMTL!EDSL!!
A!Python!tool!for!simulaBng!PyMTL!FL,!CL,!and!RTL!models!
A!Python!tool!for!translaBng!PyMTL!RTL!models!into!Verilog!
A!Python!tesBng!framework!for!model!validaBon!

! !

API! SimulaBon! Tool! TranslaBon! Tool! Model!EDSL! TesBng!Framework!

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 56 / 125

SLIDE 7

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

The PyMTL Framework

Model!

Specifica>on& Tools& Output!

Model&/&Tool&Split&

Elaborator! Model! Instance! Config! Test!&!Sim! Harness! Traces!&! VCD! SimulaBon! Tool! Verilog! TranslaBon! Tool! EDA! Toolflow! User!Tool! Output! User! Tool!

VisualizaBon! StaBc! Analysis! Dynamic! Checking! FPGA! SimulaBon! High!Level! Synthesis!

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 57 / 125

SLIDE 8

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

PyMTL 101: Traditional Model in Python

def max_unit( input_list ):! return max( input_list )!

!

[!3,!1,!2,!0!]! 3!!

f(x)!

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 58 / 125

SLIDE 9

Presentation Overview Presentation Pydgin Intro Hands-On GCD Instr

⇣ Presentation

PyMTL Intro

⌘

Hands-On Max/RegIncr Presentation ML Modeling Hands-On GCD Unit

PyMTL 101: Model in PyMTL Embedded DSL

def max_unit( input_list ):! return max( input_list )! ! class MaxUnitFL( Model ):! def init( s, nbits, nports ):! ! s.in_ = InPort[nports]( nbits )! s.out = OutPort( nbits )! ! ! @s.tick_fl! def logic():! s.out.next = max( s.in_ )!

f(x)&

[!3,!1,!2,!0!]!

f(x)!

3!!

ISCA 2015 PyMTL/Pydgin Tutorial: Python Frameworks for Highly Productive Computer Architecture Research 59 / 125

PyMTL/Pydgin Tutorial Schedule

Computer Architecture Research Abstractions

Sea!of!Transistors! ApplicaBons! Algorithms! InstrucBon!Set!Architecture! Microarchitecture! VLSI! Compilers! Academic& Research& & A!Few!! Researchers! Industry& Development& & Hundreds!of! Engineers!

Computer Architecture Research Methodologies

FuncBonal!Level! Cycle!Level! Register!Transfer!Level! Algorithm&and&ISA& Development& Design&Space& Explora>on& Area/Energy/Timing&Valida>on& and& Prototype&Development&

Modeling&Towards&Layout

Greater&& Simula>on& Speed& Greater&& Model& Detail&

Computer Architecture Research Toolflows

FuncBonal!Level! Cycle!Level! Register!Transfer!Level! Algorithm&and&ISA& Development& Design&Space& Explora>on& Area/Energy/Timing&Valida>on& and& Prototype&Development&

Different!languages,!! paKerns,!and!tools! The&Computer&Architecture& Research&Methodology&Gap

Great Ideas From Prior Frameworks

(Liberty,!Cascade,!SystemC)" "

(SystemC)! !

(Chisel,!Genesis2,!BlueSpec,!MyHDL)! !

(Cascade)" "

(Liberty,!BlueSpec)&

Consistent!interfaces!across!abstracBons! ! ! Unified!design!environment!for!FL,!CL,!RTL! ! ! ProducBve!RTL!design!space!exploraBon! ! ! ProducBve!RTL!validaBon!and!cosimulaBon! ! ! Component!and!test!bench!reuse!

What is PyMTL?

!

! !

API! SimulaBon! Tool! TranslaBon! Tool! Model!EDSL! TesBng!Framework!

The PyMTL Framework

Model!

Specifica>on& Tools& Output!

Model&/&Tool&Split&

Elaborator! Model! Instance! Config! Test!&!Sim! Harness! Traces!&! VCD! SimulaBon! Tool! Verilog! TranslaBon! Tool! EDA! Toolflow! User!Tool! Output! User! Tool!

PyMTL 101: Traditional Model in Python

def max_unit( input_list ):! return max( input_list )!

!

[!3,!1,!2,!0!]! 3!!

f(x)!

PyMTL 101: Model in PyMTL Embedded DSL

def max_unit( input_list ):! return max( input_list )! ! class MaxUnitFL( Model ):! def __init__( s, nbits, nports ):! ! s.in_ = InPort[nports]( nbits )! s.out = OutPort( nbits )! ! ! @s.tick_fl! def logic():! s.out.next = max( s.in_ )!

f(x)&

[!3,!1,!2,!0!]!

f(x)!

3!!

def max_unit( input_list ):! return max( input_list )! ! class MaxUnitFL( Model ):! def init( s, nbits, nports ):! ! s.in_ = InPort[nports]( nbits )! s.out = OutPort( nbits )! ! ! @s.tick_fl! def logic():! s.out.next = max( s.in_ )!