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Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In collaboration with Derek Lockhart (Google), and Christopher Batten 3rd RISC-V Workshop, Jan 2016 Cornell University Cornell University Computer Systems

  1. Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator Berkin Ilbeyi In collaboration with Derek Lockhart (Google), and Christopher Batten 3rd RISC-V Workshop, Jan 2016 Cornell University Cornell University Computer Systems Laboratory Computer Systems Laboratory

  2. Motivation Software Instruction-Set Architecture Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  3. Motivation Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  4. Motivation Performance Interpretive: 1-10 MIPS (1-10 days) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  5. Motivation Performance Interpretive: 1-10 MIPS (1-10 days) Typical DBT: 100s MIPS (1-3 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  6. Motivation Performance Interpretive: 1-10 MIPS (1-10 days) Typical DBT: 100s MIPS (1-3 hours) QEMU DBT: 1000 MIPS (0.5 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  7. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  8. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  9. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) Vendor Proprietary ISA Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  10. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) RISC-V Foundation RISC-V Software Instruction-Set Simulator Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  11. Motivation Productivity Performance - Develop Interpretive: 1-10 MIPS (1-10 days) - Extend Typical DBT: 100s MIPS (1-3 hours) - Instrument QEMU DBT: 1000 MIPS (0.5 hours) RISC-V Foundation RISC-V Software Specialized RISC-V Instruction-Set Simulator Specialized RISC-V Hardware 1 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  12. Productivity Performance 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  13. Productivity Performance Architectural Instruction Set Description Interpreter in C Language with DBT 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  14. Productivity Performance Architectural Instruction Set Description Interpreter in C Language with DBT 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  15. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT [Simit-ARM2006] J.D’Erricoand W.Qin. Constructing Portable Compiled Instruction-Set Simulators — An ADL-Driven Approach. DATE’06. [Wagstaff2013] H. Wagstaff, M. Gould, B. Franke, and N.Topham. Early Partial Evaluation in a JIT-Compiled, Retargetable Instruction Set Simulator Generated from a High-Level Architecture Description. DAC’13. 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  16. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Dynamic Language Interpreter in C with JIT Compiler 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  17. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Key Insight: Similar productivity-performance challenges for Dynamic Language building high-performance interpreters of Interpreter in C dynamic languages. with JIT Compiler (e.g. JavaScript, Python) 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  18. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Key Insight: Similar productivity-performance challenges for Dynamic Language building high-performance interpreters of Interpreter in C dynamic languages. with JIT Compiler (e.g. JavaScript, Python) 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  19. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Dynamic-Language RPython Dynamic Language Interpreter in C Interpreter Translation in RPython Toolchain with JIT Compiler 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  20. Productivity Performance Architectural Instruction Set [SimIt-ARM2006] Description Interpreter in C [Wagstaff2013] Language with DBT Dynamic-Language RPython Dynamic Language Interpreter in C Interpreter Translation in RPython Toolchain with JIT Compiler Meta-Tracing JIT: makes JIT generation generic across languages 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  21. Productivity Performance Architectural Instruction Set Pydgin Description Interpreter in C Language with DBT RPython Translation Toolchain 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  22. Productivity Performance Architectural Instruction Set Pydgin Description Interpreter in C Language with DBT RPython Translation Toolchain JIT ≈ DBT 2 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  23. Pydgin Architecture Description Language Architectural State State Instruction Encoding Encoding Semantics Instruction Semantics 3 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  24. Pydgin Architecture Description Language Architectural State State class State( object ): Encoding Semantics def __init__( self, memory, reset_addr=0x400 ): self.pc = reset_addr self.rf = RiscVRegisterFile() self.mem = memory # optional state if floating point is enabled if ENABLE_FP: self.fp = RiscVFPRegisterFile() self.fcsr = 0 4 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  25. Pydgin Architecture Description Language Instruction Encoding State encodings = [ Encoding Semantics # ... ['xori', 'xxxxxxxxxxxxxxxxx100xxxxx0010011'], ['ori', 'xxxxxxxxxxxxxxxxx110xxxxx0010011'], ['andi', 'xxxxxxxxxxxxxxxxx111xxxxx0010011'], ['slli', '000000xxxxxxxxxxx001xxxxx0010011'], ['srli', '000000xxxxxxxxxxx101xxxxx0010011'], ['srai', '010000xxxxxxxxxxx101xxxxx0010011'], ['add', '0000000xxxxxxxxxx000xxxxx0110011'], ['sub', '0100000xxxxxxxxxx000xxxxx0110011'], ['sll', '0000000xxxxxxxxxx001xxxxx0110011'], # ... ] 5 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  26. Pydgin Architecture Description Language Instruction Semantics State def execute_addi ( s, inst ): Encoding Semantics s.rf[inst.rd] = s.rf[inst.rs1] + inst.i_imm s.pc += 4 def execute_sw ( s, inst ): addr = trim_xlen( s.rf[inst.rs1] + inst.s_imm ) s.mem.write( addr, 4, trim_32( s.rf[inst.rs2] ) ) s.pc += 4 def execute_beq ( s, inst ): if s.rf[inst.rs1] == s.rf[inst.rs2]: s.pc = trim_xlen( s.pc + inst.sb_imm ) else: s.pc += 4 6 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  27. Pydgin Framework Interpreter Loop State def instruction_set_interpreter( memory ): Encoding Semantics state = State( memory ) while True: Pydgin Framework pc = state.fetch_pc() inst = memory[ pc ] # fetch execute = decode( inst ) # decode execute( state, inst ) # execute 7 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  28. Pydgin Framework Interpreter Loop State def instruction_set_interpreter( memory ): Encoding Semantics state = State( memory ) while True: Pydgin Framework pc = state.fetch_pc() inst = memory[ pc ] # fetch Debug on execute = decode( inst ) # decode Python execute( state, inst ) # execute Interpreter 100 KIPS 7 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  29. The RPython Translation Toolchain RPython Source State Type Inference Encoding Semantics Op � miza � on Pydgin Framework Code Genera � on Debug on RPython Python Translation Compila � on Interpreter Toolchain 100 KIPS Compiled Interpreter 8 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

  30. The RPython Translation Toolchain RPython Source State Type Inference Encoding Semantics Op � miza � on Pydgin Framework Code Genera � on Debug on RPython Python Translation Compila � on Interpreter Toolchain 100 KIPS Compiled Interpreter Pydgin Interpretive Simulator 10 MIPS 8 / 16 Pydgin for RISC-V: A Fast and Productive Instruction-Set Simulator

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