Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What - PowerPoint PPT Presentation

Roadmap 1. Instruction Set Architectures (ISA) What is CISC? What is RISC? Why did RISC prevail in the instruction set “wars”? Describe a simple RISC ISA called DLX 2. Designing a simple DLX processor: Single Cycle Implementation Multiple Cycle Implementation Lead to Pipelined Processor Design

Simplified Integer DLX Instruction Set DLX: Idealized RISC processor similar to MIPS Load/Store architecture using displacement addressing 32 bit word size aligned at word boundaries 32-bit memory addresses (aligned) Registers: • 32 32-bit Integer GPRs (Register 0, (R0), fixed at zero) R0 …. R31 • R0 is a dummy register: hardwired to value zero • 32 32-bit Floating Point Registers F0, .. F31 • Can also be treated as 16 Double Precision Registers F0, F2, …F28, , F30 • No condition codes Instructions: 1. ALU instructions: (ADD, SUB, AND, OR, …. ) RR mode: operands and results in registers RI mode: immediate 16-bit operand sign-extended to 32 bits 2. Memory reference instructions: Load (ld) and Store (sd) 3. Control instructions: conditional branch (beq, bne, bgt, ble, …….) Branch Target Address: PC+ 4 + (adjusted) 16-bit offset PC is the address of the Branch instruction

Simplified Integer DLX Instruction Set 1. ALU instructions: (ADD, SUB, AND, OR, XOR, ….) RR mode: ADD Rd, Rs, Rt | [Rd] = [Rs] + [Rt] Example:: ADD R2, R4, R5 – Rd: 5-bit field with destination register id – Rs: 5-bit field with a register id of source operand 1 – Rt: 5-bit field with a register id of source operand 2 • The 32-bit contents of registers Rs and Rt are added, and the sum is written to register Rd. RI mode: ADDI Rt, Rs, d | [Rt] = [Rs] + EXT(d) Example: ADDI R2, R4, 1000 – Rt: 5-bit field with destination register id – Rs: 5-bit field with a register id of source operand 1 – d: 16-bit immediate field holding the (constant) source operand 2 • The 16-bit value d is sign-extended to 32 bits and added to the 32 bit contents of register Rs. The sum is written to register Rt.

Simplified Integer DLX Instruction Set 2. Memory reference instructions: Load (LW) and Store (SW) LW Rt, d(Rs) | ea = EXT(d) + (Rs); (Rt) = MEM[ea] Example: LW R5, 0(R2) | Load into R5 the word whose address is stored in R2 SW R5, 1000(R2) | Address of word is 1000 + value in R2 • Reads a word from Memory at effective address [ea] and writes it to register Rt • 16-bit displacement d is sign-extended to 32 bits and added to the contents of base register Rs to get the effective address. Read memory word at effective address and load into Rt

Simplified Integer DLX Instruction Set 3. Control instructions: Branch on condition: If condition is TRUE goto Target Address; else continue with next in-line instruction • Comparison between values in two registers (e.g. beq, bne, bgt, blt, bge, ble, ) • Compare with 0 (e.g. beqz, bnez, bgtz, bltz, bgez, blez, ) beq Rs, Rt, d(PC) | Goto Target Address if contents of registers Rs and Rt are equal beqz Rs, d(PC) | Goto Target Address if contents of register Rs equals zero Target Address = PC + 4 + Extended-and-Scaled(d) 16-bit displacement d is sign-extended to 32 bits and shifted left by 2 bits (word address)

Instruction Format Examples R-R Instructions: ADD rd, rs, rt 5 5 5 6 op code 1 rs rt rd op code 2 R-I Instructions: ADDI rt, rs, d op code 1 rs rt immediate value 6 5 5 16 Load/Store/Branch Instructions: LW rt, d(rs), SW rt, d(rs), BEQ rs, rt, d(PC) op code 1 rs rt displacement 16 5 5 6

DLX Implementation Functional Units • Register File (REG) • Instruction Memory (IM) • Data memory (DM) • Arithmetic Logic Unit (ALU) • Decoder, Program Counter DataPaths Path of information in executing an instruction: sequence of FUs Timing Enforcing sequencing in the datapath

Functional Units Multi-ported Register FILE (REG) : 32 Registers 2 Read Ports (a, b) 1 Write port (c) • 5-bit id of register to be read is placed on ra (rb). Value stored in the register appears on the output port after some delay T read • 5 -bit id of register to be written placed on rc, the 32-bit data to be written put on DATA lines and the Write signal is enabled. At the rising edge of the clock the value in DATA is written to the specified destination register. (ra) ra a a R0 (rb) rb b b R1 R2 rc c (DATA) c R31 REGWrite • Up to 2 reads and 1 write can occur simultaneously in the same cycle • Increasing number of ports: • Greater concurrency in register access (+) • Area, power and access time increases (-) • Speculative register read is good for performance but has power/energy cost

Functional Units Instruction Memory (IM) and Data Memory (DM) • READ: Provide Memory Address on address lines ADDR. And enable MEMRead. Word at that address output on DATA OUT after delay T mem • WRITE: Provide Memory Address on address lines ADDR, Data to be stored is put on lines DATA in and write signal MEMWrite. Word stored into memory location at clock edge. Signals should be stable at least T mem before the clock edge. MEMRead • Assume Single Ported Memory in base design DATA OUT ADDR IM DATA in or DM MEMWrite

Functional Units ALU • Input Ports A, B for source operands • Output port provides results after delay T ALU • Provides single operand and two-operand ALU instructions (+, -, &, !, etc) • Function to be performed provided in control input ALU op A RESULT ALU B ALU op Decoder: Combinatorial Circuit that generates control signals from instruction PC: Register holds address of current instruction. Changes value at next clock edge

Hypothetical Single-cycle Implementation of DLX Assume Each instructions completes in 1 (LONG!!) clock cycle • Registers have stable values following rising clock edge During clock cycle: 1. Instruction is read from Instruction memory (IM) 2. Decoded and control signals for use during the cycle are generated 3. Register values are read 4. ALU outputs are generated 5. Data Memory is read or written for Load or Store 6. New PC value is computed • All registers and memory are updated at next rising clock edge.

Datapaths R-R Instruction: a, b: Read port DATA c: Write port (rs) rs a p Register ALU rt (rt) File q b + rd c ALUop 4 RWrite ALUop PC IM RWrite add Rd, Rs, Rt Decode

Datapath: Register-Immediate R-Imm : a, b: Read port a, b: Read port DATA c: Write port c: Write port (rs) rs a d: Imm data p Register ALU rt File q b + c rt ALUop 4 RWrite d (32) EXT d (16) ALUop PC IM RWrite addi Rt, Rs, Imm Decode

Datapaths lw Instruction: DATA (rs) rs a p Register ALU ADDR rt DM File q b + c rt ALUop 4 d(32) RWrite EXT MREAD d(16) ALUop PC IM RWrite lw Rt, d(Rs) Decode MREAD

Datapaths R-R, R-Imm, lw : MUX RDataSel DATA (rs) rs a p Register ALU rt (rt) DM File q MUX b + d c rd MUX ALUop ALUSel 4 WSel RWrite EXT MREAD ALUop PC IM Rwrite ALUSel Decode RDataSel WSel MREAD

Datapaths R-R instruction : MUX RDataSel DATA rs (rs) a p Register ALU rt (rt) DM File q MUX b + d c rd MUX ALUop ALUSel 4 WSel RWrite EXT MREAD ALUop PC IM Rwrite ALUSel add Rd, Rs, Rt Decode RDataSel WSel MREAD

Datapaths Reg-Immediate : MUX RDataSel DATA rs (rs) a p Register ALU (rt) rt DM File q MUX b + d c MUX ALUop ALUSel 4 WSel RWrite EXT MREAD ALUop PC IM Rwrite ALUSel addi Rt, Rs, Imm Decode RDataSel WSel MREAD

Datapaths lw Instruction: MUX RDataSel DATA rs (rs) a p Register ALU (rt) rt DM File q MUX b + d c MUX ALUop ALUSel 4 WSel RWrite EXT MREAD ALUop PC IM Rwrite ALUSel lw Rt, d(Rs) Decode RDataSel WSel MREAD

Datapaths sw Instruction: MWRITE (rs) rs a p ADDR Register ALU rt File d q b DM + (rt) c ALUop DATA 4 d(16) EXT ALUop PC IM sw Rt, d(Rs) Decode MWRITE

Datapaths R-R, R-Imm, MUX lw, sw : MWRITE RDataSel DATA (rs) rs a p Register ALU rt (rt) File q ADDR MUX DM b + d c ALUSel ALUop rd MUX 4 WSel RWrite DATA EXT ALUop MREAD PC IM Rwrite ALUSel Decode RDataSel WSel MREAD MWRITE

Datapaths beq Instruction: beq Rs, Rt, d + (rs) rs << a p Register ALU rt z File (rt) q EXT b + c ALUop 4 d(16) ALUop MUX PC IM Decode PCSel PCSel Branch