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Preallocating Resources for Distributed Memory based FPGA Debug Robert Hale & Brad Hutchings FPGA Debug - Logic Analyzer 1. External? 2. Internal? Time Resources Xilinx Internal Logic Analyzer (ILA) FPGA with 94% of LUT

  1. Preallocating Resources for Distributed Memory based FPGA Debug Robert Hale & Brad Hutchings

  2. FPGA Debug - Logic Analyzer 1. External? 2. Internal? ● Time ● Resources

  4. Xilinx Internal Logic Analyzer (ILA)

  5. FPGA with 94% of LUT resources utilized: Xilinx ILA: Where will the embedded logic analyzer fit?

  6. Can we debug at all?

  7. Xilinx Shift Register LUT (SRL)

  8. Distributed Memory (DIME) Debug

  9. Process JTAG

  10. 4-bit Counter Output

  11. DIME Debug - Research Questions 1. Can we enable internal debug when the device is 90%+ utilized? 2. How will DIME trace buffers impact the user circuit (timing)? 3.What is the ideal organization of DIME buffers on the device?

  12. How do we organize those LUTs?

  13. DIME Preallocation - Research Questions 1. Will this hurt the performance of the user circuit? 2. Will this improve performance of the combined DIME + user circuit?

  14. Benchmarks LC3 Sudoku RPulseG RNG uFIFO

  15. Preallocation - Affect User Design? ● Implementation: No impact ● Timing: Max 0.1ns

  16. Preallocation - Affect DIME Debug? LC3 90% LC3 90% (with preallocation)

  17. Results RPulseG Sudoku uFIFO RNG

  18. LC3 Can we lengthen DIME trace buffers? RPulseG Sudoku uFIFO RNG

  19. Conclusion ● DIME debug: 90%+ utilized designs ● Preallocating FPGA resources for DIME debug: ○ Almost no impact on original design ○ Reduce timing penalty (up to 2ns) ○ Increase trace buffer count (up to ~3x) ● DIME trace buffers can be lengthened

  20. Thank you Research supported by Xilinx Research Labs Robert Hale robert.hale@byu.edu

  21. <This Page Intentionally Left Blank>

  22. Contributions ● Pros/cons of preallocating LUTs for DIME trace buffers ● 5 unique (duplication-based) benchmarks ● Extending DIME trace buffers to 256 bits

  23. Process

  25. Experiments <describe experiments> <diagram?>

  26. DIME Debug - Research Questions 1. How many user signals can I access? 2. How big are the trace buffers? 3. What is the impact to the user circuit (timing)?

  27. Pinterest FPGA:

  28. LC3 Can we lengthen DIME trace buffers? RPulseG Sudoku uFIFO RNG

  29. Real FPGA: Where will the embedded logic analyzer fit?

  30. Experiments Will preallocating resources improve the distributed-memory debug process? ● Timing? ● Debug bits?

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