IC Project and Verifica7on Physical Verifica7on Joachim - - PowerPoint PPT Presentation

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

HT2011/VT2012 ¡ ¡

IC ¡Project ¡and ¡Verifica7on ¡

Physical ¡Verifica7on ¡ ¡ ¡ ¡Joachim ¡Rodrigues ¡

¡

¡

• Dept. ¡of ¡Electrical ¡and ¡Informa7on ¡Technology

¡ Lund ¡University ¡ ¡ ¡

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Prac7cali7es ¡

• Reports need to be emailed to (latest April 23rd):

joachim.rodrigues.lu@analysis.urkund.se

• After having recieved feedback from your supervisors

the report needs to be resubmitted within one week (if required)

• Report will be assessd
• After report approval you will get approved on the

project part with passing grade (9ECTS)

• Final grade will be received after verification part

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Post-­‑Synthesis ¡Verifac7on ¡

Your design needs to pass post-synthesis simulation (Modelsim)

– The sdf file needs to be read into Modelsim – Simulation time or number of test patterns may be reduced – Only applicable for small designs – Industry uses Formal Verification You have done that by now

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Physical ¡Verifac7on ¡(FPGA) ¡

Your design needs to be synthesized for FPGA

– FPGA timing information needs to be included in the simulation – You may discover some surprises (inferred latches) – FPGA needs to be programmed

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Physical ¡Verifac7on ¡(FPGA) ¡

Analyzer FPGA Logic Analyzer

Data from the analyzer needs to be compared with RTL response (Matlab) You will measure single bit values which will confirm your simualtion results More detailed intructions will be given in the lab

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Available ¡Resources ¡

FPGA

– Xilinx Spartan 3/Virtex-II

Logic Analyzer

– Agilent HP 16702 +new one

You need to sign up for a time slot (2 weeks) in the labs on 4th floor.

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Prepara7on ¡

Implement your design on FPGA

• Perform a post-route simulation
• If you use large memories you need cut the

size to fit it on FPGA Measurements can be quickly done if everything is running on FPGA

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Project ¡Finaliza7on ¡

Verification report

• Needs to be submitted on the last day of the

time slot.

• Revisions: need to be handed in 1 week after

feedback was received.

Joachim Rodrigues, EIT, Lund University, Sweden www.es.lth.se/home/jrs joachim.rodrigues@eit.lth.se

Questions?