PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame - - PowerPoint PPT Presentation

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PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame - - PowerPoint PPT Presentation

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PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame Rate Converter Colin Osborne / Ralf Karge PNX85500 Single Chip LCD TV System Hot Chips 2009 August, 25, 2009 Presentation Outline Introduction System Integration More TV

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SLIDE 1

PNX85500 Single Chip LCD TV System

with integrated 120Hz HD Frame Rate Converter

Colin Osborne / Ralf Karge PNX85500 Single Chip LCD TV System Hot Chips 2009 August, 25, 2009

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SLIDE 2

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 2

Presentation Outline

Introduction System Integration

– More TV System on a Chip – PNX85500 TV Solution

Design Challenges

– Architecture – Memory Bandwidth and Latency – Verification and Emulation

High-lighted Features Conclusions

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SLIDE 3

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 3

Introducing the TV550 System

TV550 System comprises the world’s first Digital TV SoC in C045: PNX85500

  • Channel demodulators, networking (USB, HDMI, Ethernet, SD card reader),

120 Hz, H.264 HD decoding, advanced Picture Quality Algorithms, etc. Extremely high level of functional integration

  • Full application (networking, H.264 HD decoding, advanced gfx, FRC, …) all
  • n 2x16-bit DDR2 footprint!

Smallest memory requirement for the total system

  • Avoid expensive EMI protection with built-in spread-spectrum on both LVDS

as well as DDR interfaces Drives industry’s lowest cost-of-ownership/bill-of-material

  • Minimize upfront development costs and time-to-market for global rollout
  • One development, one PCB line, one test set up

Enables development for global chassis roll out thanks to low system costs

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SLIDE 4

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 4

Introduction System Integration

– More TV System on a Chip – PNX85500 TV Solution

Design Challenges

– Architecture – Memory Bandwidth and Latency – Verification and Emulation

High-lighted Features Conclusions

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SLIDE 5

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 5

TV550 System Integration

CVBS,Y/C, RGB L/R L/R L,R YCbCr

NXP

PNX8543

MIPS32@300 MHz Pixel OSD, TV Control, HDMI,USB,PC-AVI

DDR2 256MB FLASH 128 MB

PNX8543

LVDS-2 CVBS SPDIF L,R Audio Amplifier DVB-C Channel Decoder TDA10024 Tuner TDA18272 SPDIF RGB, HV L/R PCMCIA NXP TFA9810 32 bit DDR2-666 TS Low-IF

Analog IF IP TDA8296

CVBS/SIF

Ethernet MAC DVB-T Channel Decoder TDA10048 Silicon Tuner Switch TDA9996

CI+

HDMI Switch

HD 1080p 100/120Hz 50/60Hz

NXP

PNX5120

Frame Rate Conversion

PNX85500

32 bit DDR2-666 DDR2 128MB

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SLIDE 6

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 6

TV550 System Integration

CVBS,Y/C, RGB L/R L/R L,R YCbCr

NXP

PNX8543

MIPS32@300 MHz Pixel OSD, TV Control, HDMI,USB,PC-AVI

DDR2 256MB FLASH 128 MB

PNX8543

LVDS-2 CVBS SPDIF L,R Audio Amplifier DVB-C Channel Decoder TDA10024 Tuner TDA18272 SPDIF PCMCIA NXP TFA9810 32 bit DDR2-666 TS Low-IF

Analog IF IP TDA8296

CVBS/SIF

Ethernet MAC DVB-T Channel Decoder TDA10048 Silicon Tuner Switch TDA9996

CI+

HDMI Switch

HD 1080p 100/120Hz 50/60Hz

NXP

PNX5120

Frame Rate Conversion

RGB, HV L/R

PNX85500

32 bit DDR2-666 DDR2 128MB

NXP

PNX85500

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SLIDE 7

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 7

TV550 – FRC 120Hz FULL HD

DVB-T, CI+, PAL/SECAM, IP

TV5 V550

HDMI

DIGITAL AUDIO OUT DIGITAL AUDIO IN

HDMI

TFA9810

HDMI HDMI

PN PNX8 X8550x

DDR2 128 MB FLASH ASH 64 MB

CI+

Ethernet

PHY TDA9996 switch

USB SB

DDR2 128 MB TDA18272 Si Tuner

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SLIDE 8

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 8

TV550 – FRC 120Hz FULL HD

DMB-T/ATSC/ISDB-T, PAL/SECAM/NTSC, IP

TV5 V550

HDMI

DIGITAL AUDIO OUT DIGITAL AUDIO IN

HDMI

TFA9810

HDMI HDMI

PN PNX8 X8550x

DDR2 128 MB FLASH ASH 64 MB

Ethernet

PHY TDA9996 switch

USB SB

TDA18272 Si Tuner DDR2 128 MB Channel Demod

Optional China CI+

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SLIDE 9

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 9

LVDS_TX MIPS24K CAI

MIPS24K – Control Network

Video Scaler (1) Video Composition Pipe (1) R W R W R W SPDIF GPIO

AVDSP – Control Network

HDMI_RX Audio Decoding Audio Processor USB R W AV-DSP R W I2C Video Input Processor Video Composition Pipe (2) R DENC Interrupts R W I2S R BRIDGE R 2D Drawing R W Digital Video Decoder R W R W R W W Transport Stream Input PC_AVI R W Frame Rate Converter R W W ETHERNET R W Video Scaler (2) R W FLASH_CTRL W Channel Decode MCU_DDR (32bit) R W MPEG Demux R W PC_AVI R W A A R

DMA Read

W

DMA Write Key

Scatter/Gather DMA R W PC_AVI MEM_ARB RTC GFX_SCALER R W SPI R W SD Card R W R/W

Control Network

R W

PNX85500 Block Diagram

UART JTAG RESET CLOCKS Interrupts SYS_CTRL

DMA Network DMA Network

Generic Control and Interconnect Digital Broadcast / Transport Stream Audio Processing Video Processing and Graphics

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SLIDE 10

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 10

Introduction System Integration

– More TV System on a Chip – PNX85500 TV Solution

Design Challenges

– Architecture – Memory Bandwidth and Latency – Verification and Emulation

High-lighted Features Conclusions

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SLIDE 11

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 11

Organizational Complexity

World-wide multi-site project

– UK, Netherlands, Germany, France, India, Israel, USA

Number of IPs

– Approx 100 IP blocks (85% NXP-internal)

Compute infra metrics

– 15 TBytes of disk space – 3 TBytes of RAM for SoC Integration

Caen Southampton Hamburg Chicago San Jose Eindhoven Haifa Bangalore

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SLIDE 12

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 12

Integrating many different functions

Analogue Standards Decoder MIPS24K Digital Audio Decoder Audio Post-Processing Audio Presentation Connectivity Interfaces Audio and Video Capture MPEG Demux & Descrambler MPEG/H.264 Video Decoder Flexible Video Decoder Graphics Rendering Picture Quality Processing Video Presentation Auto Picture Control Frame Rate Conversion

Function Examples Established HW functions Analogue audio/video decoding High performance HW functions Video scaling & composition Control processing Generic operating system Flexible DSP Audio & video feature processing High performance DSP Motion Accurate Picture Processing

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SLIDE 13

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 13

Challenging Bandwidth and Latency Needs

Audio Processor Digital Video Decoder MIPS24K Critical Embedded Control CPU Critical Tolerant FRC Co- processor Tolerant FRC Processor Critical Tolerant AVDSP Processor Critical Memory Subsystem with Arbitration and Buffering Video Comp. Pipe(s) Tolerant Video Scaler(s) Tolorant

Cost pressure only allows 2 x 16 DDR2-1066

  • Limiting gross bandwidth to 4.2 Gbytes/sec
  • Originally the TV550 system was expected to need 64-bit DDR interface

Requiring high-bandwidth and low-latency

  • Processors for flexible processing: requiring low-latency to minimise cache miss penalty
  • Hardware traffic mostly predictable: requiring high-bandwidth

Innovative solutions

  • Processors supported by specific arbitration settings in infrastructure
  • Hardware units and VLIW pre-fetch memory accesses
  • Local caches/buffers
  • Video streaming between IP functions
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SLIDE 14

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 14

Assuring fast Silicon Bring-Up

Extensive suite of verification methods

Various abstraction levels in simulation of

– IP functionality and connectivity – SoC infrastructure performance

Emulation of representative Software and Hardware

– 300 million gates of IC emulation capacity – System tuning and performance sign-off – 300 - 400 k frames of HD video before tape out

Advance system software development Emulation All main use-cases had been brought up on the emulator before silicon

– Software was ready when silicon arrived – Arbitration and tuning settings had been verified => Very rapid silicon bring-up

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SLIDE 15

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 15

PNX85500 Silicon

  • TSMC's 45nm Low Power (LP)

process technology

  • 27 mm Flip Chip BGA Package
  • Power Consumption < 7 Watt
  • No active cooling required
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SLIDE 16

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 16

Introduction System Integration

– More TV System on a Chip – PNX85500 TV Solution

Design Challenges

– Architecture – Memory Bandwidth and Latency – Verification and Emulation

High-lighted Features Conclusions

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SLIDE 17

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 17

Complex SoC made up by Complex IPs

Example: Video Scaler

VCAR MPEG Artefact Reduction STDI De-interlacer TNR Temporal Noise Reduction PCOR Projection data for film detector AHSC Horizontal scaler

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SLIDE 18

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 18

Complex SoC made up by Complex IPs

Example: Video Composition Pipe

PCTI Peaking-based Color Transient Improvement VSHR Video Sharpening SKCR Skin-tone Control BSKY Blue-Sky Enhancement DI2D 2-Dimensional Backlight Dimming

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SLIDE 19

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 19

Motion Accurate Picture Processing

Film Judder Cancellation + Motion Blur Reduction

24 Hz film

A B

Original Movie 24 frames per second

A A A B B

Typical TV at 50 or 60 frames per second (with ‘movie judder’)

A

PNX85500 output at 120 frames per second; after movie judder removal

2 3 4 5 B 7 8 9 10

High quality smooth, natural-looking motion

  • analysed and created
  • in real-time, for HD video content
  • at 120 frames per second
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SLIDE 20

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 20

Improved Picture Quality at Reduced Power

2D Local Dimming Processing

Video input Video output Backlight output Perceived output

Video on backlight

+

=

PNX85500

Histogram FRC Processor Image Analysis Backlight calculation

Reduce LCD TV’s backlight power by about 50% Significant increase

  • f contrast and black

level Histogram measurement and pixel processing done in HW-IP Flexible processing

  • f VLIW processor

for image analysis and backlight calculation

Video Gain

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SLIDE 21

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 21

Introduction System Integration

– More TV System on a Chip – PNX85500 TV Solution

Design Challenges

– Architecture – Memory Bandwidth and Latency – Verification and Emulation

High-lighted Features Conclusions

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SLIDE 22

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 22

Conclusions

PNX85500: the world’s first DTV SoC in 45nm

  • Very high level of integration
  • Award-winning 120 Hz processing in front-end TV SoC
  • Enabling global chassis, single platform

Performance critical

  • Iterative analysis and optimisation through design cycle
  • Solving challenging demands on memory latency

Verification challenge

  • Very high level of integration creates challenges in interdependency and complexity
  • Extensive use of prototyping using emulation and FPGA

First silicon arrived in Q1 2009

  • Successful customer demonstrations within 2 weeks of first silicon!

What’s next?

  • Higher integration levels, lower system cost
  • Improved picture quality, increased frame rates and resolution
  • New video features
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SLIDE 23

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 23

Questions

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SLIDE 24

25-Aug-2009 PNX85500 / HotChips / C.Osborne, R. Karge 24