PNX85500 Single Chip LCD TV System with integrated 120Hz HD Frame Rate Converter Colin Osborne / Ralf Karge PNX85500 Single Chip LCD TV System Hot Chips 2009 August, 25, 2009
Presentation Outline Introduction System Integration – More TV System on a Chip – PNX85500 TV Solution Design Challenges – Architecture – Memory Bandwidth and Latency – Verification and Emulation High-lighted Features Conclusions 2 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Introducing the TV550 System TV550 System comprises the world’s first Digital TV SoC in C045: PNX85500 Extremely high level of functional integration • Channel demodulators, networking (USB, HDMI, Ethernet, SD card reader), 120 Hz, H.264 HD decoding, advanced Picture Quality Algorithms, etc. Smallest memory requirement for the total system • Full application (networking, H.264 HD decoding, advanced gfx, FRC, …) all on 2x16-bit DDR2 footprint! Drives industry’s lowest cost-of-ownership/bill-of-material • Avoid expensive EMI protection with built-in spread-spectrum on both LVDS as well as DDR interfaces Enables development for global chassis roll out thanks to low system costs • Minimize upfront development costs and time-to-market for global rollout • One development, one PCB line, one test set up 3 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Introduction System Integration – More TV System on a Chip – PNX85500 TV Solution Design Challenges – Architecture – Memory Bandwidth and Latency – Verification and Emulation High-lighted Features Conclusions 4 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
TV550 System Integration DDR2 DDR2 256MB 128MB PNX85500 PCMCIA HD 1080p DVB-C Channel 100/120Hz TS Decoder 50/60Hz CI+ 32 bit TDA10024 DVB-T Channel DDR2-666 Decoder 32 bit TDA10048 DDR2-666 NXP Low-IF Tuner Analog IF IP PNX5120 TDA18272 TDA8296 Frame Rate CVBS/SIF Silicon Tuner Conversion LVDS-2 NXP CVBS,Y/C, PNX8543 CVBS L/R MIPS32@300 MHz RGB Pixel OSD, TV Control, L,R L/R HDMI,USB,PC-AVI YCbCr SPDIF PNX8543 SPDIF L,R NXP TFA9810 RGB, HV Audio Amplifier L/R Ethernet MAC HDMI Switch Switch FLASH TDA9996 128 MB 5 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
TV550 System Integration DDR2 DDR2 256MB 128MB PNX85500 PCMCIA HD 1080p DVB-C Channel 100/120Hz TS Decoder 50/60Hz CI+ 32 bit TDA10024 DVB-T Channel DDR2-666 Decoder 32 bit TDA10048 DDR2-666 NXP Low-IF Tuner Analog IF IP PNX5120 TDA18272 TDA8296 Frame Rate CVBS/SIF Silicon Tuner Conversion LVDS-2 NXP NXP CVBS,Y/C, PNX8543 CVBS PNX85500 L/R MIPS32@300 MHz RGB Pixel OSD, TV Control, L,R L/R HDMI,USB,PC-AVI YCbCr SPDIF PNX8543 SPDIF L,R NXP TFA9810 RGB, HV Audio Amplifier L/R Ethernet MAC HDMI Switch Switch FLASH TDA9996 128 MB 6 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
TV550 – FRC 120Hz FULL HD DVB-T, CI+, PAL/SECAM, IP TV5 V550 DDR2 DDR2 FLASH ASH 128 MB 128 MB 64 MB TDA18272 Si Tuner PN PNX8 X8550x TFA9810 CI+ TDA9996 switch DIGITAL AUDIO IN PHY HDMI HDMI HDMI Ethernet HDMI USB SB DIGITAL AUDIO OUT 7 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
TV550 – FRC 120Hz FULL HD DMB-T/ATSC/ISDB-T, PAL/SECAM/NTSC, IP TV5 V550 DDR2 DDR2 FLASH ASH 128 MB 128 MB 64 MB TDA18272 Si Tuner PNX8 PN X8550x Channel Demod TFA9810 TDA9996 switch DIGITAL AUDIO IN PHY HDMI HDMI HDMI Ethernet HDMI USB SB DIGITAL AUDIO OUT Optional China CI+ 8 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
PNX85500 Block Diagram MCU_DDR (32bit) R A R MEM_ARB SYS_CTRL FLASH_CTRL W Digital Video Interrupts W R Decoder R W MIPS24K Interrupts W GPIO R AV-DSP W CLOCKS R Frame W A RESET Rate W Converter LVDS_TX R/W R MIPS24K – Control Network JTAG I2C W R AVDSP – Control Network MPEG Demux W R DENC UART PC_AVI R Scatter/Gather W W DMA Transport R R Stream Input W Video Scaler (1) W PC_AVI CAI R Video DMA Network R Composition R W USB Pipe (1) W R Video Channel R 2D Drawing W Input Processor Decode W R R Key Video Scaler (2) GFX_SCALER W W Video R ETHERNET R Composition HDMI_RX Control Network W Pipe (2) R SPI Audio Decoding W W PC_AVI DMA Network W Audio Processor R SPDIF SD Card R DMA Read R W W RTC W DMA Write I2S R BRIDGE Digital Broadcast / Transport Stream Video Processing and Graphics Generic Control and Interconnect Audio Processing 9 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Introduction System Integration – More TV System on a Chip – PNX85500 TV Solution Design Challenges – Architecture – Memory Bandwidth and Latency – Verification and Emulation High-lighted Features Conclusions 10 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Organizational Complexity World-wide multi-site project Chicago Southampton Caen Hamburg – UK, Netherlands, Germany, France, India, Israel, USA Number of IPs – Approx 100 IP blocks (85% NXP-internal) San Jose Eindhoven Haifa Bangalore Compute infra metrics – 15 TBytes of disk space – 3 TBytes of RAM for SoC Integration 11 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Integrating many different functions Function Examples Established HW functions Analogue audio/video decoding High performance HW functions Video scaling & composition Control processing Generic operating system Flexible DSP Audio & video feature processing High performance DSP Motion Accurate Picture Processing Analogue MPEG Picture Quality MIPS24K Standards Demux & Processing Decoder Descrambler Digital Audio MPEG/H.264 Frame Rate Decoder Video Decoder Conversion Audio and Audio Flexible Auto Picture Video Post-Processing Video Decoder Control Capture Connectivity Audio Graphics Video Interfaces Presentation Rendering Presentation 12 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Challenging Bandwidth and Latency Needs Cost pressure only allows 2 x 16 DDR2-1066 • Limiting gross bandwidth to 4.2 Gbytes/sec • Originally the TV550 system was expected to need 64-bit DDR interface Requiring high-bandwidth and low-latency • Processors for flexible processing: requiring low-latency to minimise cache miss penalty • Hardware traffic mostly predictable: requiring high-bandwidth Innovative solutions • Processors supported by specific arbitration settings in infrastructure • Hardware units and VLIW pre-fetch memory accesses • Local caches/buffers • Video streaming between IP functions Memory Subsystem with Arbitration and Buffering Critical Critical Tolerant Critical Tolerant Critical Tolerant Tolerant Tolorant Embedded Digital Video FRC FRC Co- AVDSP Audio Video Comp. Video MIPS24K Control CPU Decoder Processor processor Processor Processor Pipe(s) Scaler(s) 13 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Assuring fast Silicon Bring-Up Extensive suite of verification methods Various abstraction levels in simulation of – IP functionality and connectivity – SoC infrastructure performance Emulation of representative Software and Hardware – 300 million gates of IC emulation capacity – System tuning and performance sign-off – 300 - 400 k frames of HD video before tape out Emulation Advance system software development All main use-cases had been brought up on the emulator before silicon – Software was ready when silicon arrived – Arbitration and tuning settings had been verified => Very rapid silicon bring-up 14 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
PNX85500 Silicon • TSMC's 45nm Low Power (LP) • Power Consumption < 7 Watt process technology • No active cooling required • 27 mm Flip Chip BGA Package 15 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Introduction System Integration – More TV System on a Chip – PNX85500 TV Solution Design Challenges – Architecture – Memory Bandwidth and Latency – Verification and Emulation High-lighted Features Conclusions 16 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Complex SoC made up by Complex IPs Example: Video Scaler STDI De-interlacer VCAR AHSC MPEG Artefact Horizontal scaler Reduction PCOR TNR Projection data Temporal Noise for film detector Reduction 17 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Complex SoC made up by Complex IPs Example: Video Composition Pipe PCTI Peaking-based Color Transient Improvement SKCR Skin-tone Control VSHR BSKY Video Sharpening Blue-Sky Enhancement DI2D 2-Dimensional Backlight Dimming 18 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
Motion Accurate Picture Processing Film Judder Cancellation + Motion Blur Reduction B A 24 Hz film Original Movie 24 frames per second B B A A A Typical TV at 50 or 60 frames per second (with ‘movie judder’) A 2 3 4 5 B 7 8 9 10 PNX85500 output at 120 frames per second; after High quality smooth, natural-looking motion movie judder removal - analysed and created - in real-time, for HD video content - at 120 frames per second 19 PNX85500 / HotChips / C.Osborne, R. Karge 25-Aug-2009
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