P Performance Analysis of f A l i f Ultra-Scaled InAs HEMTs - - PowerPoint PPT Presentation

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P Performance Analysis of f A l i f Ultra-Scaled InAs HEMTs Neerav Kharche 1 , Gerhard Klimeck 1 , Dae-Hyun Kim 2,3 , Jess. A. del Alamo 2 , and Mathieu , , Luisier 1 1 Network for Computational Nanotechnology and 1 N t k f C t ti l N

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SLIDE 1

P f A l i f Performance Analysis of Ultra-Scaled InAs HEMTs

Neerav Kharche1, Gerhard Klimeck1, Dae-Hyun Kim2,3, Jesús. A. del Alamo2, and Mathieu , , Luisier1

1N t

k f C t ti l N t h l d

1Network for Computational Nanotechnology and

Birck Nanotechnology Center, Purdue University

2Microsystems Technology Labs, Massachusetts

c osyste s ec

  • ogy

abs, assac usetts Institute of Technology

3Teledyne Scientific & Imaging, LLC

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SLIDE 2

Motivation: Towards III-V MOSFET

  • Strained channel
  • New gate

dielectrics

  • Device geometries
  • Channel materials
  • High-k dielectrics

2015-2019 Research

dielectrics High k dielectrics III-V channel devices

Acknowledgement: Robert Chau, Intel

Low-power & high-speed

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SLIDE 3

Motivation: Why III-V HEMTs?

III V E t di l t t t ti

  • III-V: Extraordinary electron transport properties
  • HEMTs: Very similar structure to MOSFETs except high-κ

dielectric layer y

  • Excellent to Test Performances of III-V material without

interface defects

  • Excellent to Test Simulation Models
  • Excellent to Test Simulation Models

– Develop simulation tools and benchmark with experiments P di t f f lt l d d i – Predict performance of ultra-scaled devices

2007: 40nm 2008: 30nm

D.H. Kim et al., EDL 29, 830 (2008)

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SLIDE 4

Outline

M i i

  • Motivation
  • Modeling Approach

– Real-space EM simulator including gate leakage – Atomistic tight-binding m* Realistic description of simulation domain (gate – Realistic description of simulation domain (gate geometry)

  • Comparison to Experiments Lg=30, 40, 50nm

Comparison to Experiments Lg 30, 40, 50nm

– Material parameters, Id-Vgs, Id-Vds

  • Scaling Considerations for Lg=20nm

g

g

– Channel thickness, Insulator thickness, Gate metal work function

  • HEMT Simulator on nanoHUB.org
  • Conclusion and Outlook
slide-5
SLIDE 5

Outline

M i i

  • Motivation
  • Modeling Approach

– Real-space EM simulator including gate leakage – Atomistic tight-binding m* Realistic description of simulation domain (gate – Realistic description of simulation domain (gate geometry)

  • Comparison to Experiments Lg=30, 40, 50nm

Comparison to Experiments Lg 30, 40, 50nm

– Material parameters, Id-Vgs, Id-Vds

  • Scaling Considerations for Lg=20nm

g

g

– Channel thickness, Insulator thickness, Gate metal work function

  • HEMT Simulator on nanoHUB.org
  • Conclusion and Outlook
slide-6
SLIDE 6

Device Geometry and Simulation Domain

I t i i d i

Source Drain

Lg Extrinsic device

  • Intrinsic device

– Near gate contact Self consistent 2D

InAlAs

n+ Cap n+ Cap

InP etch stop

Gate

δ-doped layer

– Self consistent 2D Schrodinger-Poisson – Electrons injected

e

R R

InAs InGaAs

from all contacts

Si l ti D i

Source Drain

S

R

D

R

  • M. Luisier et. al., IEEE

Transactions on Electron Devices

InP Substrate

  • Extrinsic source/drain

t t

Simulation Domain: Intrinsic device

Transactions on Electron Devices,

  • vol. 55, p. 1494, (2008).

contacts – Series resistances RS and RD RS and RD

  • R. Venugopal et.al., Journal of

Applied Physics, vol. 95, p. 292, (2004).

slide-7
SLIDE 7

Gate Geometry and Gate Leakage Current

1

(a)

3 2 Flat Gate

(b)

1) Include series resistances

s d gs ext gs

R I V V  

int

 

d s d ds ext ds

R R I V V   

int

2) Include gate leakage current 3) Incl de the proper gate

g g

 

d s d ds ds

) ( ) (

G D S G D S

S S S C H E           

Curved Gate

3) Include the proper gate geometry flat (a) or curved (b) Gate leakage reduced in curved gate device

slide-8
SLIDE 8

Accurate Effective Mass Calculation

Full Band Transport: Effective Mass Transport: Full-Band Transport:

  • Strain, Disorder, Non-

parabolicity, BTBT Effective Mass Transport:

  • Gate leakage,

Computationally efficient

  • No gate leakage,

Computationally very intensive

  • Parabolic bands, No

disorder, Wrong quantization levels Import m*

~ 4 nm

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SLIDE 9

Outline

M i i

  • Motivation
  • Modeling Approach

– Real-space EM simulator including gate leakage – Atomistic tight-binding m* Realistic description of simulation domain (gate – Realistic description of simulation domain (gate geometry)

  • Comparison to Experiments Lg=30, 40, 50nm

Comparison to Experiments Lg 30, 40, 50nm

– Material parameters, Id-Vgs, Id-Vds

  • Scaling Considerations for Lg=20nm

g

g

– Channel thickness, Insulator thickness, Gate metal work function

  • HEMT Simulator on nanoHUB.org
  • Conclusion and Outlook
slide-10
SLIDE 10

Transfer Characteristics: Id-Vgs

Parameter Initial Final parameter set Parameter Initial Final parameter set 30 40 50 Lg [nm] 30, 40, 50 34.0 42.0 51.25 Lg [nm] 30, 40, 50 34.0 42.0 51.25 tins [nm] 4 3.6 3.8 4.0 ΦM [eV] 4.7 4.66 4.69 4.68 m*ins (InAlAs) 0.075 0.0783 0.0783 0.0783 m*buf (InGaAs) 0.041 0.0430 0.0430 0.0430

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SLIDE 11

Output Characteristics: Id-Vds

Conclusion:

  • Good agreement for all Lg’s

g

  • Less ballistic at Lg=50nm
  • Use models and material

parameters to design ultra- parameters to design ultra scaled devices (Lg=20nm)

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SLIDE 12

Outline

M i i

  • Motivation
  • Modeling Approach

– Real-space EM simulator including gate leakage – Atomistic tight-binding m* Realistic description of simulation domain (gate – Realistic description of simulation domain (gate geometry)

  • Comparison to Experiments Lg=30, 40, 50nm

Comparison to Experiments Lg 30, 40, 50nm

– Material parameters, Id-Vgs, Id-Vds

  • Scaling Considerations for Lg=20nm

g

g

– Channel thickness, Insulator thickness, Gate metal work function

  • HEMT Simulator on nanoHUB.org
  • Conclusion and Outlook
slide-13
SLIDE 13

What can be changed?

  • Gate geometry
  • Channel thickness

scaling: tInAs Better control of scaling: tInAs

  • Insulator thickness

scaling: tins surface potential

  • Metal work function

engineering: ΦM Gate leakage reduction and E-mode operation

L 20 Lg=20nm

Φ

Gate

InAs In0.52Al0.48As

urce rain

In0.53Ga0.47As

tins t ΦM

InAs

Sou Dr

tInAs

slide-14
SLIDE 14

InAs (Channel) Layer Thickness

InAs Channel Scaling:

  • Better electrostatic control

I

– lower SS – larger ION/IOFF ratio Increase of transport m*

IOFF increases

  • Increase of transport m*

– reduced vinj, higher Ninv => higher ION g

ON

  • Increase of gate leakage

current

Gate

– ION/IOFF ratio saturates

InAs

urce rain

In0.53Ga0.47As

t

Gate

InAs In0.52Al0.48As

Sou Dr

tInAs

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SLIDE 15

InAlAs (Insulator) Layer Thickness

InAlAs Insulator Scaling:

  • Better electrostatic control
  • Better electrostatic control

(due to larger Cox)

  • Increase of gate leakage

gate leakage

g g current – larger IOFF l SS – larger SS – smaller ION/IOFF ratio

Gate

InAs

urce rain

In0.53Ga0.47As

Gate

tins

InAs In0.52Al0.48As

Sou Dr

slide-16
SLIDE 16

Work Function Engineering

Work Function Increase:

  • Shift towards enhancement

mode

  • Decrease of gate leakage current
  • Allows for thinner insulator layer

– steeper SS – larger ION/IOFF ratio

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SLIDE 17

Parameters and Performances Summary

(1) Gate (2) Channel (3) Insulator (4) Metal work (1) Gate geometry (2) Channel thickness (3) Insulator thickness (4) Metal work function Improved Higher gate Gate leakage gate control leakage reduction SS I /I SS ION/IOFF

Lg=20nm

1 2 3 4 1 2 3 4 2 1 3

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SLIDE 18

Outline

M i i

  • Motivation
  • Modeling Approach

– Real-space EM simulator including gate leakage – Atomistic tight-binding m* Realistic description of simulation domain (gate – Realistic description of simulation domain (gate geometry)

  • Comparison to Experiments Lg=30, 40, 50nm

Comparison to Experiments Lg 30, 40, 50nm

– Material parameters, Id-Vgs, Id-Vds

  • Scaling Considerations for Lg=20nm

g

g

– Channel thickness, Insulator thickness, Gate metal work function

  • HEMT Simulator on nanoHUB.org
  • Conclusion and Outlook
slide-19
SLIDE 19

HEMT Simulator on nanoHUB.org

OMEN_FET:

  • 2-D Schrödinger-Poisson solver
  • Real-space effective mass

t t t d l quantum transport model

  • Injection (white arrows) from

Source, Drain, and Gate contacts HEMTs Single and Double Gate

  • HEMTs, Single- and Double-Gate

devices

  • Electron transport in Si and III-V
  • Ballistic transport (no Scattering)
  • Ballistic transport (no Scattering)
  • Current Flow Visualization

h // HUB / l / hf http://nanoHUB.org/tools/omenhfet Run your own simulations!

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SLIDE 20

Conclusion and Outlook

Extrinsic device Extrinsic device

  • Multiscale Modeling Approach

– EM transport including gate l k

Simulation Domain: Intrinsic device

leakage – m* from tight-binding

  • Good Agreement with
  • Good Agreement with

Experiments

  • Scaling Considerations for 20nm

Device

  • HEMT Simulator Deployed on

nanoHUB org nanoHUB.org

  • Challenges and Future Directions

– S/D contacts, high-k insulator,

Lg=20nm

, g , scattering, interface traps

Vd=0.50 V Vd=0.05 V

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SLIDE 21

Thank You!

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SLIDE 22

Transfer Characteristics: Id-Vgs (2)

L [nm] SS [mV/dec] DIBL I /I V [cm/s] Lg [nm] SS [mV/dec] DIBL [mV/V] ION/IOFF Vinj [cm/s] 30 Expt. 107 169 0.47×103 Sim. 105 145 0.61×103 3×107 40 Expt. 91 126 1.38×103 Sim. 89 99 1.86×103 3.11×107 Sim. 89 99 1.86 10 3.11 10 50 Expt. 85 97 1.80×103 Sim. 89 91 1.85×103 3.18×107

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SLIDE 23

Gate Leakage Mechanism

  • Electrons tunnel from gate into
  • Electrons tunnel from gate into

InAs channel

  • Tunneling barriers

InAlAs and InGaAs – InAlAs and InGaAs – Position dependent barriers

  • Current crowding at edges (due to

lower tunneling barriers)

  • Barriers modulated by ΦM

ΦM

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SLIDE 24

Work Function Engineering (2)

Characteristics:

  • Same Gate Overdrive

h i i

ΦM =4.7 eV ΦM =5.1 eV

– same thermionic current (source to drain)

  • Gate Fermi levels
  • Gate Fermi levels

shifted by ∆ΦM

– different tunneling barrier height barrier height

  • ΦM =4.7 eV

– tunnel through InAlAs only InAlAs only – larger Ig

  • ΦM =5.1 eV

– tunnel through – tunnel through InAlAs and InGaAs – lower Ig