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Overview Recap Operator Sharing Introduction to Structured VLSI Design FSMD VHDL V Counters Joachim Rodrigues Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V Joachim Rodrigues, EIT, LTH,

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SLIDE 1

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Introduction to Structured VLSI Design ‐ VHDL V

Joachim Rodrigues

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Overview

  • Recap
  • Operator Sharing
  • FSMD
  • Counters

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Ram vs Register

RAM characteristics

– RAM cell designed at transistor level – Cell use minimal area – Is combinatorial and behaves like a latch – For mass storage – Requires a special interface logic

Register characteristics

– DFF (may) require much larger area – Synchronous – For small, fast storage – e.g., register file, fast FIFO

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Register File

Registers are arranged as an 1‐d array

  • Each register is accessible with an address
  • Usually 1 write port (with write enable signal)
  • May have multiple read ports
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SLIDE 2

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Strictly Structured VHDL

  • How is it done?

– Local signals (r, rin) are stored in records and contain all registered values. – All outputs are stored in a entity specific record type declared in a global interface package – enables re‐use. – Use a local variable (v) of the same type as the registered values. – reset handling moves to combinatorial part.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Strictly Structured VHDL‐Advantages

Adding a signal in traditional style

  • Add port in entity declaration
  • Add signal to sensitivity list
  • Add port in component declaration
  • Add port in component instantiation

Adding a signal in Strictly Structured VHDL methodology

  • Add element in record declaration

DUT DUT

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Structured VHDL‐Stored signals

Adding a stored signal in traditional style

  • Add two signals (current, next)
  • Add signal to sensitivity list
  • Add reset value
  • Update on clock edge

Adding a signal in Structured VHDL methodology

  • Add element in declaration record

Comb Next Current Comb rin r

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Configuration

  • Testbench is reused by declaring a different configuration
  • A configuration may realize different architectures, memories, etc.
  • Examples:

– A synthesizable model / behavorial model – A synthesizable model / gate‐level model

Syntax:

configuration configuration_name of entity_name is for architecture_name for label|others|all: comp_name use entity [lib_name.]comp_entity_name(comp_arch_name) | use configuration [lib_name.]comp_configuration_name [generic map (...)] [port map (...)] ; end for; ... end for; end configuration_name;

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SLIDE 3

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Operator sharing

Circuit complexity of VHDL operators varies

  • Arithmetic operators

– Large implementation – Limited optimization by synthesis software

  • Manual optimization may be forced by operator

sharing in RTL – Operator sharing – Functionality sharing

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Operator sharing cont’d

Multiplexing network are mutually exclusively: – Only one result is routed to output – Selected sig assignment (case statement) with select_expression select sig_name <= value_expr_1 when choice_1, value_expr_2 when choice_2, value_expr_3 when choice_3, . . . value_expr_n when choice_n;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example I

Original code:

r <= a+b when boolean_exp else a+c;

Revised code:

src0 <= b when boolean_exp else c; r <= a + src0;

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example II

Original code:

process(a,b,c,d,...) begin if boolean_exp_1 then r <= a+b; elsif boolean_exp_2 then r <= a+c; else r <= d+1; end if end process;

Revised code:

process(a,b,c,d,...) begin if boolean_exp_1 then src0 <= a; src1 <= b; elsif boolean_exp_2 then src0 <= a; src1 <= c; else src0 <= d; src1 <= "00000001"; end if; end process; r <= src0 + src1;

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

FSMD

  • Combination of controller and datapth
  • Usefule to realize an algortihm in hardware
  • Example

Add 4 numbers Divide the sum by 8 Round the result Task: Convert the algorithm into a combinational circuit

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example

VHDL code

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example

Problems with dataflow implementation:

– Can only be applied to trivial algorithm – Not flexible – Can we just share one adder in a time‐multiplexing fashion to save hardware resources?

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Register Transfer Methodology

Recipe

– Use register to store intermediate data and imitate variable – Use a datapath to realize all register operations – Use a control path (FSM) to specify the order of register operation – The system is specified as sequence of data manipulation/transfer among registers – Realized by FSM with a datapath (FSMD)

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Basic RT operation

Interpretation:

– At the rising edge of the clock, the

  • utput of registers rsrc1 rsrc2 etc. are

available. – The output are passed to a combinational circuit that performs f( ). – At the next rising edge of the clock, the result is stored into rdest

Basic form:

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Multiple Operations

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Controller

FSM is sufficient to control RT operation

– State transition is on clock‐by‐clock basis – FSM can enforce order of execution – FSM allows branches on execution sequence

Normally represented in an extended algorithmic state machine chart, known as ASMD (ASM with datapath) chart

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Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

ASM chart

  • Used for larger state diagrams, often are easier to

interpret.

  • Conditions for a proper state diagram are

automatically satisfied.

  • Easily converted to other forms.

ASM charts do not enumerate all the possible inputs and outputs. Only the inputs that matter and the

  • utputs that are asserted are indicated.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example

New value of r1 is only available when the FSM exits s1 state

same operations

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Registers in Decision Box

New value of r1 is only available when the FSM exits s1 state

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Basic FSMD Architecture

FSM

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SLIDE 7

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Design Example

  • Sequential Multiplier

– 7*5 =

Pseudo code: ASMD code

7+7+7+7+7

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Design Example cont’d

Input:

– a_in, b_in: 8‐bit unsigned – clk, reset – start: command

Output:

– r: 16‐bit unsigned – ready: status

ASMD chart Default RT operation:

– keep the previous value – Parallel execution in op state

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Design Example cont’d

Recipe to build a data path

– List all RT operations – Group RT operation according to the destination register – Add combinational circuit/mux – Add status circuits

RT operation with the r register

r ←r

(idle state)

r ←0

(load/op state)

r ←r+b

(op state) RT operation with the n register

n ←n

(idle state)

n ←b_in

(load/ab0 state)

n ←n‐1

(op state) RT operation with the a register

a ←a

(idle state)

a ←a_in

(load/ab0 state)

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Design Example cont’d

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SLIDE 8

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Design Example cont’d

  • Continue with remaining

registers

FSM

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example Operator Sharing

case when s1 d1 <= a*b; ... when s2 d1 <= b*c; ... when s3 d1 <= a*c; ... end case;

d1←a*b s1 d1←a*b s2 d1←a*b s3

Synthesis tool may infere 3 multipliers Expensive in hardware

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Example Operator Sharing

case when s1 d1 <= a*b; ... when s2 d1 <= b*c; ... when s3 d1 <= a*c; ... end case; case when s1 in1 <= a; in2 <= b; ... when s2 in1 <= b; in2 <= c; ... when s3 in1 <= a; in2 <= c; ... end case; m_out <= in1*in2; How can the number of multipers be reduced?

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Counters

  • Binary
  • Gray counter
  • Ring counter
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SLIDE 9

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Binary Counter

Binary counter:

– State follows binary counting sequence – Use an incrementor for the next‐state logic

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Gray Counter

Gray counter:

– State changes one bit at a time – Use a Gray incrementor

VHDL can be provided on request

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Ring Counter

Circulate a single 1, e.g., 4‐bit ring counter: 1000, 0100, 0010, 0001

– n patterns for n‐bit register – Output appears as an n‐phase signal

Non self‐correcting design

– Insert “0001” at initialization and circulate the pattern in normal operation

Fastest counter

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Ring Counter cont’d

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SLIDE 10

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Deadlines

  • Assignment 2 is due no later than Friday 25th
  • Source code needs to be provided
  • Code must be readable, i.e., use indent etc.

Code Code Code Code Format: Landscape

Bad example Good example

  • No Lecture on Friday

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V

Synthesis Summary

Screen dump of the synthesis summary is needs to be handed in with the code.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se VHDL V