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Overview Homework Circuit Timing Introduction to Structured VLSI - - PowerPoint PPT Presentation

Dec 25, 2023 146 likes •235 views

Overview Homework Circuit Timing Introduction to Structured VLSI Design Controller Datapath Control Structures Dependency Graph Precedency Graph VHDL Presentation of Assignment 2 Joachim Rodrigues Joachim Rodrigues,

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SLIDE 1

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Introduction to Structured VLSI Design ‐ Control Structures

Joachim Rodrigues

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Overview

  • Homework
  • Circuit Timing
  • Controller Datapath
  • Dependency Graph
  • Precedency Graph
  • VHDL
  • Presentation of Assignment 2

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

FSM Exercise (”Homework”)

Marge wants to install an alarm that triggers as soon as somebody enters the kitchen. The alarm should have several alert levels.

  • level0: Neither Homer nor Bart is in the kitchen
  • level1: Bart but not Homer is in the kitchen
  • level2: Homer but not Bart is in the kitchen
  • level3: Homer and Bart are in the kitchen

To detect who enters or leaves the kitchen 2 sensors g1 and g0 are installed in the door frame as depicted. The sensors emit a ‘1’ as soon as their reflection is

  • interrupted. If Bart enters the kitchen only g0 will emit a ‘1’. Homer is always

leaning forward when he is entering the kitchen, and, thus, g1 will always be interrupted before g0. Once they have decided to go into the kitchen they will go through the door. However, if they are in the kitchen they always can leave, e.g., level3 changes to level2. The size of Homers hips and belly prevent them from entering the kitchen simultaneously. The clock frequency is 1MHz.

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Classification of digital circuits

This course

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SLIDE 2

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Classification

  • SGT (synchronous globally timed):

– Global clock, – Fixed module latencies, One BIG FSM

  • SLT (synchronous locally timed):

– Global clock, Hierarchy of (local) FSMs – Variable module latencies (start‐ & finish signals)

  • ALT (asynchronous locally timed):

GALS (globally asynchronous locally synch.

– Local clocks – Synchronization + protocol at interfaces

All asynchronous:

– Handshake components – Channels (data+req+ack) everywhere

  • AGT (asynchronous globally timed):

Nonsense Discrete time Contineous time

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Classification, schematical

6

rs rf clk clk rs rf clk2 clk1 rs rf

SGT SLT (ALT) GALS (ALT) All asynchronous

FSM + datapath FSM1+ datapath1 FSM2+ datapath2 FSM1'+ datapath1' FSM2'+ datapath2' Control1”+ datapath1” Control2”+ datapath2”

s s s = Synchronizer Data connections not shown

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Combinatorial Circuit

))) ( ), ( ( )), ( ( ( ) ( x h x f p x f g p x r =

f

h

1

p

g

2

p

) (x r x

  • Expensive (no reuse of operator modules)
  • Not flexible (fixed function)
  • Modules idle for large periods of time
  • P1 and P2 realize the same function

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Datapath

f

h

g

p

fD gD hD pD

A

AEN CLK xD

B

BEN CLK

x ) (x r

Controlled by drivers and register enable signals. What do we need to do if we want to reuse p? Controller+ DP Tri‐state buffer

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SLIDE 3

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

SGT module: FSM + Data path

CLK

) (x r

FSM DataPath

fD gD pD hD AEN BEN

x

xD

In principle: One global controller ! Control signals from previous slide

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

SLT module: FSM + Datapath

CLK

) (x r

FSM DataPath

rS

fD gD pD hD AEN BEN

x

rF

xD

Start and finish signals. Local FSMs inside modules. Hierarchy of FSMs Enables modular design

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

SLT‐module Interface

CLK

) (x r

FSM DataPath

rS fD gD pD hD AEN BEN

x

rF xD

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

SLT‐module Interface

CLK

) (x r

rS

x

rF CLK

rS

x

rF

) (x r

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SLIDE 4

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

The Recipe

1. Given a data‐path 2. Identify precedence constraints inherent in expression (data dependency graph)

Essential precedence constraints

3. Identify precedence constraints imposed by:

– Data‐path topology non‐essential constraints – Components essential constraints

4. Precedence graph with

– Register loads – All precedence constraints

5. Design the FSM

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Combinatorial Circuit = Dependency Graph

))) ( ), ( ( )), ( ( ( ) ( x h x f p x f g p x r =

f

h

g

1

p

) (x r x

2

p

  • utput of each operation needs to secured in a register

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Final Precedence Graph

))) ( ), ( ( )), ( ( ( ) ( x h x f p x f g p x r =

f

h

g

1

p

) (x r x

B h →

B p →

1

B p → A x → A f → A g → 2

p

Only one bus: f→A and h→B in 2 cycles Why p1→B before g→A? A holds input for g, hence f →A Because p takes inputs from both A and B. If we do g →A first p sees new inputs

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Final Precedence Graph

))) ( ), ( ( )), ( ( ( ) ( x h x f p x f g p x r =

f

h

g

1

p

) (x r x

B h →

B p →

1

B p → A x → A f → A g → 2

p

Total: 6 clock cycles 1 2 3 5 6 4 !! One datapath: Only one register can be loaded during one clock cycle!!

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SLIDE 5

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Improved Datapath

f

g

p

fD gD pD

h

hD

A

AEN CLK xD

B

BEN CLK

x ) (x r

Difference: operation h is driven by register B

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Precedence Graph (improved DP)

))) ( ), ( ( )), ( ( ( ) ( x h x f p x f g p x r =

f

h

g

1

p

) (x r x

h B ←

1

p B ← p B ←

x B x A ← ←

f A ← g A ← 2

p

Same as before:except: No required ordering of B←f and A←f But still only one bus. x is loaded into B

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Improved Datapath

f

g

p

fD gD pD

h

hD

A

AEN CLK xD

B

BEN CLK

x (x r

1st cycle: x →A,B

f

h g

1

p

) (x r

h B ←

1

p B ← p B ←

x B x A ← ← f A ← g A ← 2

p

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Improved Datapath

f

g

p

fD gD pD

h

hD

A

AEN CLK xD

B

BEN CLK

x (x r

2nd cycle: h → B

f

h g

1

p

) (x r

h B ←

1

p B ← p B ←

x B x A ← ← f A ← g A ← 2

p

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SLIDE 6

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Improved Datapath

f

g

p

fD gD pD

h

hD

A

AEN CLK xD

B

BEN CLK

x (x r

3rd cycle: f→A

f

h g

1

p

) (x r x

h B ←

1

p B ← p B ←

x B x A ← ← f A ← g A ← 2

p

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Improved Datapath

f

g

p

fD gD pD

h

hD

A

AEN CLK xD

B

BEN CLK

x ) (x r

2 5 3 4

Now: TCL>TCLK

Propagation delays in time units

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Precedence Graph (improved DP)

f

h

g

1

p

) (x r x

h B ←

1

p B ← p B ← 2

p

2 5 3 3 4 f p1 p2 g A B A B A

1 2 3 4 5 6 7 8 9 10 11 12 13

h

14 15

B B

f A ← g A ←

x B x A ← ← Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Using a SLT controller

  • What if g–module with latency = 2 cycles becomes

available?

  • Redesign and reimplement the FSM
  • If FSM:

– responds to gS‐signal – produces gF‐signal and

then optimization of g–module is possible without any change of the FSM.

  • This is SLT‐design
  • Still need to distribute zero‐skew clock to

everywhere.

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SLIDE 7

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Making an SLT module

f

g

p

fD gD pD

h

hD

A

AEN CLK xD

B

BEN CLK

x ) (x r

gS gF

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

Making an SLT module

CLK

) (x r

FSM DataPath

rS

fD gD pD hD AENBEN

x

rF

xD

gF gS

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

SLT‐module Interface

CLK

) (x r

FSM DataPath

rS fD gD pD hD AEN BEN

x

rF xD

Joachim Rodrigues, EIT, LTH, Introduction to Structured VLSI Design jrs@eit.lth.se Control Structures

SLT‐module interface

CLK

) (x r

xS

x

rF CLK

xS

x

rF

) (x r