1-8.1 1-8.2 Outcomes • I know the difference between combinational and sequential logic and can name examples of each. • I understand latency, throughput, and at least 1 technique to Spiral 1 / Unit 8 improve throughput • I can identify when I need state vs. a purely combinational Transistor Implementations function CMOS Logic Gates – I can convert a simple word problem to a logic function (TT or canonical form) or state diagram • I can use Karnaugh maps to synthesize combinational functions with several outputs • I understand how a register with an enable functions & is built • I can design a working state machine given a state diagram • I can implement small logic functions with complex CMOS gates 1-8.3 1-8.4 DeMorgan’s Theorem F = (X+Y) + Z • (Y+W) To find F’, invert both sides of the equation and then use DeMorgan’s theorem to simplify… F = (X+Y) + Z • (Y+W) DEMORGAN'S THEOREM
1-8.5 1-8.6 Generalized DeMorgan’s Theorem DeMorgan’s Theorem Example F’(X 1 ,…,X n ,+,•) = F(X 1 ’ ,…,X n ’ ,•,+) • Cancel as many bubbles as you can using DeMorgan’s theorem. To find F’, swap AND’s and OR’s and complement each literal. However, you must maintain the original order of operations. F = (X+Y) + Z • (Y+W) Note: This parentheses doesn’t matter (we are just OR’ing X’, Y, and the Fully parenthesized to following subexpression) F = X+Y + (Z • (Y+W)) show original order of ops. AND’s & OR’s swapped F = X•Y • (Z + (Y•W)) Each literal is inverted 1-8.7 1-8.8 Evolution of transistor in ICs • BJT invention, Bell Labs, 1947 • Single transistor, TI, 1958 • CMOS gate, Fairchild, 1963 – First processor, Intel, 1970 • Very Large Scale Integration, 1978 With focus on MOS Transistors – Up to 20k transistor SEMICONDUCTOR TECHNOLOGY • Ultra Large Scale Integration, 1989 – More than 1 million per chip • System-on-Chip, 2002-2015 – Millions to several billion transistors
1-8.9 1-8.10 Invention of the Transistor Growth Rate • Vacuum tubes ruled in first half of 20 th century • 53% compound annual growth rate over 50 Large, expensive, power-hungry, unreliable years • No other technology has grown so fast so long • 1947: first point contact transistor • Driven by miniaturization of transistors – John Bardeen and Walter Brattain at Bell Labs – Smaller is cheaper, faster, lower in power! – See Crystal Fire – Revolutionary effects on society by Riordan, Hoddeson [Moore65] Electronics Magazine 1-8.11 1-8.12 Minimum Feature Size Intel 4004 Micro-Processor 1971 1000 transistors 1 MHz operation
1-8.13 1-8.14 ARM Cortex A15 Intel Core I7 2 nd Gen. Intel Core i7 Extreme Processor for ARM Cortex A15 in 2011 to 2013 desktops launched in Q4 of 2012 • 4 cores per cluster, two clusters per chip • #cores/#threads: 6/12 • Technology node: 22nm • Technology node: 32nm • Clock speed: 2.5 GHz • Clock speed: 3.5 GHz • Transistor count: Over one billion • Transistor count: Over one billion • Cache: Up to 4MB per cluster • Cache: 15MB • Addressable memory: up to 1TB • Addressable memory: 64GB • Size: 52.5mm by 45.0mm • Size: 52.5mm by 45.0mm mm 2 14 1-8.15 1-8.16 Cortex-A72 IBM z13 Storage Controller
1-8.17 1-8.18 Annual Sales Cost per Transistor • >10 19 transistors manufactured in 2008 cost: – 1 billion for every human on the planet ¢-per-transistor 1 Fabrication capital cost per transistor (Moore’s law) 0.1 0.01 0.001 0.0001 0.00001 0.000001 0.0000001 1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012 1-8.19 1-8.20 Internet Traffic Growth TRANSISTOR BASICS
1-8.21 1-8.22 Semiconductors Transistors As Switches • Transistor act as a form of switch (on / off) • Different physical structures lead to different kinds of transistors – Bipolar Junction Transistor (BJT) • Initial technology back in the late 40's – 60's – Metal-Oxide-Semiconductor _________________ Transistor (MOSFET) • Dominates the digital IC market today • All transistors essentially function similarly with 3 nodes/terminals: – 1 node serves as the _______ value allowing current to flow between the other 2 nodes (on) or preventing current flow between the other 2 nodes (off) – Example: if the switch input voltage is 5V, then current is allowed to flow between the other nodes A Switch Current can flow Input based on voltage (Hi or Lo of input switch Voltage) B 1-8.23 1-8.24 Semiconductor Material • Semiconductor material is not a great conductor material in its pure form – Small amount of free charge • Can be implanted (“________”) with other elements (e.g. boron or arsenic) to be more conductive – Increases the amount of _______ charge + - - + - + + + + - - + - - - + - + - + - + - + - __-Type Silicon Pure Silicon __-Type Silicon (Doped with arsenic) (Doped with boron) Electron donors Electron acceptors
1-8.25 1-8.26 Silicon Lattice and Dopant Atoms Transistor Types p-type n-type p-type • Bipolar Junction Transistors (BJT) + + - – ______ or _____ silicon structure + – Small _______ into very thin base layer - + + controls large currents between emitter and + collector emitter base collector – However the fact that it requires a current npn BJT into the base means it burns power (______) and thus ________ how many we can • Pure silicon: 3-D lattice of atoms (a cubic crystal) and a poor integrate on a chip (i.e. density) _________ __________ conductor Gate Input • Metal Oxide Semiconductor Field Effect • Conductivity can be raised by adding either donors or acceptor Transistors conductive - – __________: Group V dopant impurities, which have more free polysilicon - – nMOS and pMOS MOSFETS electrons than silicon - - – Voltage applied to insulated gate controls + • The resulting material is called n-type + current between source and drain + n-type – Group III dopants impurities which have lack of electrons • Gate input requires no __________ current…thus p-type low power! • The resulting material is called p-type We will focus on MOSFET in this class N-type MOSFET 1-8.27 1-8.28 NMOS Transistor Physics NMOS Transistor Physics • Transistor is started by implanting two n-type silicon • A thin, insulator layer (silicon dioxide or just “oxide”) areas, separated by p-type is placed over the silicon between source and drain n-type silicon (extra Source Input Drain Output negative charges) - Source Drain - Input Input - L - W - - - - + + + Insulator Layer + + + n-type silicon (extra (oxide) negative charges) p-type silicon p-type silicon (“extra” positive charges) (“extra” positive charges)
1-8.29 1-8.30 NMOS Transistor Physics NMOS Transistor Physics • A thin, insulator layer (silicon dioxide or just “oxide”) • _______ voltage is placed over the silicon between source and drain (charge) at the gate Gate Input • Conductive polysilicon material is layered over the input repels the Source Input + Drain Output oxide to form the gate input extra positive + + n-type charges in the p- + + Gate Input type silicon Source Input Drain Output + + + + - - - - - • Result is a negative- charge channel conductive - polysilicon + + + + p-type - between the source negatively-charge positive charge input and drain - - channel “repelled” + + Insulator Layer + n-type silicon (extra (oxide) negative charges) p-type silicon (“extra” positive charges) 1-8.31 1-8.32 NMOS Transistor Physics NMOS Transistor Physics • Electrons can flow • If a _____ voltage through the (negative charge) is Gate Input Gate Input negative channel placed on the gate, Source Input + Drain Output Source Input - Drain Output from the source + no channel will - + n-type - n-type - - input to the drain + develop and no - - - + - - - output - current will flow - + + + + - - - - - - - - - - - - - + + + - • The transistor is - • The transistor is - - + _____ _____ + + + + + + p-type p-type Negative channel between No negative channel source and drain = between source and drain Current flow = No current flow
1-8.33 1-8.34 PMOS vs. NMOS • PMOS transistors can also be made that are on when the gate voltage is ____ and off when it is _____ Gate Input Gate Input Source Input + Drain Output Source Input - + - + n-type - p-type - + + - - + + - Understanding physical constraints - + - + + + + + - - - - - + - + CMOS TRANSISTOR LEVEL - - - - - + + -+ + + - + - + - + IMPLEMENTATION + + + + p-type - - - - n-type Negative channel "Positive" channel between source and between source and drain = Current flow drain = Current flow NMOS PMOS 1-8.35 1-8.36 NMOS Transistors in Series/Parallel NMOS and PMOS Transistors Connection NMOS Transistors • NMOS conducts when gate input • Transistors can be thought as a switch is at a high voltage (logic ‘1’) controlled by its gate signal 1 0 • NMOS switch closes when switch control input Current Flows No Current Flows (Large resistance between (Small resistance between is high source and output ) source and output ) NMOS (On if G=1) • PMOS conducts when gate input A B is at a low voltage (logic ‘0’) PMOS Transistors F = 1 if _______ 1 F A 0 1 B Current Flows No Current Flows 1 F = 1 if _______ F (Small resistance between (Large resistance between Indicates a source and output) source and output) P-type PMOS (On if G=0)
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