On the Greater Acceptance of Functional Test of PCB Assemblies. - - PowerPoint PPT Presentation

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On the Greater Acceptance of Functional Test of PCB Assemblies. - - PowerPoint PPT Presentation

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On the Greater Acceptance of Functional Test of PCB Assemblies. Billy Fenton & Chris Hammond EBTW 2005, Tallinn, Estonia Slide 1

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SLIDE 1

Slide 1 EBTW 2005, Tallinn, Estonia

  • On the Greater Acceptance of Functional Test
  • f PCB Assemblies.

Billy Fenton & Chris Hammond

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SLIDE 2

Slide 2 EBTW 2005, Tallinn, Estonia

  • “Functional test is set to re-emerge as the primary test method

for assembled printed circuit boards.”

Bernard Sutton, GenRad Europe -- Test & Measurement World, 10/1/1999

“…board access for electrical test will continue to be at a premium and imaging inspection will help fill the gap. But, ultimately, functional testing and/or BIST will have to provide electrical verification.”

NEMI Roadmap, 2002 Edition.

Is there a problem?

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SLIDE 3

Slide 3 EBTW 2005, Tallinn, Estonia

  • Disappearing Test Access

Area-Array Packaging (e.g. BGA) Increasing Board Operating Speeds Board Strain? Lead-free solder? Hidden Vias

Other Issues, now above the horizon

Complexity Cost

The BIG Paradox - Boards becoming more complex, with limited test access, and test cost must be lowered with less available test tools!

Why?

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SLIDE 4

Slide 4 EBTW 2005, Tallinn, Estonia

  • Electrical Test Methods

MDA ICT Boundary Scan Functional Test

  • Rack/Stack, PXI, VXI
  • BIT
  • CPU Emulation
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SLIDE 5

Slide 5 EBTW 2005, Tallinn, Estonia

  • The Rise

A component test, not a system test. Test Programming using the netlist and ATPG. Diagnostics to component or node level. Automatic Coverage Report(?)

The Decline?

Test Access IC Test

The Rise & Fall(?) of ICT/MDA

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SLIDE 6

Slide 6 EBTW 2005, Tallinn, Estonia

  • The Rise

Test programming from netlist and BSDL. Diagnostics to pin level. Automatic coverage report.

The Limitations

Digital Only – limits coverage. DFT required – can limit coverage. Will security prevent it being a panacea?

The Rise of BST

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SLIDE 7

Slide 7 EBTW 2005, Tallinn, Estonia

  • The Reluctant Rise

Test Programming is slow and difficult. Extensive UUT knowledge needed. This is exacerbated by increasing complexity. Diagnostics are poor. No coverage report.

So Why Now?

Test access is not an issue. Test coverage is high. DFT is low.

The Reluctant Rise of FT

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SLIDE 8

Slide 8 EBTW 2005, Tallinn, Estonia

  • ICT/MDA/BST advantages are FT disadvantages – ATPG, Diagnostics, Coverage

report. But, on newer boards, FT can go where ICT/MDA/BST cannot go, but it lacks the advantages that made these methods attractive. So, what we need is a FT, that provides ATPG, diagnostics, and coverage

  • reports. Otherwise the acceptance of FT will be slow.

FT as a supplement or replacement to traditional electrical type tests???

FT for Electrical Test??

ICT/MDA/BST FT Electrical Test Functional Test

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SLIDE 9

Slide 9 EBTW 2005, Tallinn, Estonia

  • Initial Architecture

Uses CPU Emulation. Standard Architecture Boards.

3 Steps

ATPG using a known-good board. Using the BOM to:

  • Create diagnostics.
  • Generate a coverage report.

Summary of our Approach

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SLIDE 10

Slide 10 EBTW 2005, Tallinn, Estonia

  • 1. ATPG for FT?
  • 1. Boot good UUT
  • 2. Run ATPG
  • ATPG has a library of

chipset drivers.

  • It searches the UUT

for known devices.

  • It then extracts the

correct chipsets drivers

  • r generic tests, and

assembles a test program.

  • Undetected chips can

be manually added.

  • User can maintain their
  • wn libraries also.

Chipset Library

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SLIDE 11

Slide 11 EBTW 2005, Tallinn, Estonia

  • Chipset Test Driver (FTDL??)
  • 1. Header Information
  • Description
  • Revision
  • Relevance
  • ID Sequence
  • 2. Learn Sequence
  • Information to extract from known good board. This is stored in some

variables.

  • 3. Generation Sequence
  • Chipset test sequence. Information extracted under 2 is inserted as required.
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SLIDE 12

Slide 12 EBTW 2005, Tallinn, Estonia

  • ATPG Example

PXA 255 ASP SDRAM Flash Audio Codec USB Controller

1. CPU Test. 2. ASP Initialise. 3. Memory Controller Initialise. 4. Bus Test. 5. SDRAM Test. 6. Flash Test. 7. USB Access Test. 8. USB connection and/or transfer test. 9. Audio Codec Access Test.

  • 10. Audio generation &

measurement test.

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SLIDE 13

Slide 13 EBTW 2005, Tallinn, Estonia

  • Boards are becoming more complex, but skill level of

technicians is often reducing. Approaches:

Don’t!! Technician Skill

  • Low skilled labour
  • Low cost products

‘Shotgun’

  • Quality
  • Cost

Historical Information

  • If available, and if recorded

Guided Fault Isolation Probabalistic Methods

  • 2. Diagnostics for FT?
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SLIDE 14

Slide 14 EBTW 2005, Tallinn, Estonia

  • Guided Fault Isolation (GFI)

Traditional GFI used probing, but this is often not possible on modern boards. During development, test execution is related to a block diagram, and suggested fixes and help can be associated with specific test failures. Additonally, a PCB layout can be loaded to locate suggested fixes.

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SLIDE 15

Slide 15 EBTW 2005, Tallinn, Estonia

  • Probabalistic Methods

During the test development stage:

Use netlist to extract BOM. Associate components with tests, and include failure probability, and identify which tests are the primary test(s) for each component.

During diagnosis:

If a test fails each associated component is scored appropriately. After overall test completion each component is given a final score. Method TBD. A list of components is presented, the one with the highest score is the most likely defect. Real-time data could be used to adjust probabilities.

Primary Test? Probability BOM Filter

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SLIDE 16

Slide 16 EBTW 2005, Tallinn, Estonia

  • Diagnostic Example

74ACT04 5% U20 17C51 Audio Codec 15% U6 Intel PXA255 80% U5 Description Score Component

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SLIDE 17

Slide 17 EBTW 2005, Tallinn, Estonia

  • 3. Test Coverage Report for FT?

What is test coverage?

Fault universe represents all possible faults. Coverage is the % of coverable faults. How does this relate to different test methods. For FT how do you define the fault universe??? How do you know what faults are covered by a particular functional test? Must tests be weighted? Etc. It’s all largely subjective.

FT coverage report

Is a % style report meaningless? But, it can be what the customer wants? Is a yes/no report more meaningful, possibly with a high/medium/low coverage metric? Can this be extracted from the BOM/Test Matrix?

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SLIDE 18

Slide 18 EBTW 2005, Tallinn, Estonia

  • Coverage Report Example
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SLIDE 19

Slide 19 EBTW 2005, Tallinn, Estonia

  • PC Style – Notebook, Server, Embedded.

PowerPC Intel PXA Series (for PDA & Display Centric Apps) Intel IXP (for networking apps) TI OMAP (PDA/Smartphone) Etc., Etc.

Suitable Boards?

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SLIDE 20

Slide 20 EBTW 2005, Tallinn, Estonia

  • Discretes.

ATPG for non-library components. Diagnostic are probabilistic. Report is not the familiar %.

Deficiencies

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SLIDE 21

Slide 21 EBTW 2005, Tallinn, Estonia

  • Adding custom components. Clearer definition of FTDL?

Netlist Analysis

Automatic block diagram generation Determining component complexity automatically

Can it be extended to other FT approaches?

Further Work

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SLIDE 22

Slide 22 EBTW 2005, Tallinn, Estonia

  • As test access becomes more difficult, inspection, BIST, and

FT will become more important. FT need to incorporate some of the advantages of ICT/MDA and BST.

ATPG. Diagnostics to component level. Automatic generation of a test coverage report.

Is this a real problem? Can it be solved? Is greater effort needed to define the approach, and/or to consolidate the various test approaches?

Conclusions