on simulated annealing in eda
play

On Simulated Annealing in EDA A tribute to Prof. C. L. Liu at ISPD - PowerPoint PPT Presentation

On Simulated Annealing in EDA A tribute to Prof. C. L. Liu at ISPD 2012 Martin D.F. Wong Department of Electrical and Computer Engineering University of Illinois at Urbana Champaign 1 ICCAD Panel on Simulated Annealing 1987 ICCAD Panel:


  1. On Simulated Annealing in EDA A tribute to Prof. C. L. Liu at ISPD ‐ 2012 Martin D.F. Wong Department of Electrical and Computer Engineering University of Illinois at Urbana ‐ Champaign 1

  2. ICCAD Panel on Simulated Annealing 1987 ICCAD Panel: “Is Simulated Annealing Practical for CAD?” 2

  3. SA Research in Liu’s Group 1988 3

  4. Preface of the Book “We hope that our experiences with the techniques we employed, some of which indeed bear certain similarities for different problems, could be useful as hints and guides for other researchers in applying the method To the solutions of other problems.” 4

  5. Studied Many Problems Channel Routing Pin Assignment Gate Matrix Layout ICCAD ‐ 85 ICCD ‐ 85, INTEGRATION ‐ 87 ICCAD ‐ 86 PLA Folding Floorplan Design Array Optimization CICC ‐ 85,JSSC ‐ 87 DAC ‐ 86,ICCAD ‐ 87 DAC ‐ 87 5

  6. DAC ‐ 86 6

  7. DAC ‐ 86 7

  8. Methodology • Significant reduction in solution space size • Keep optimal solutions 8

  9. Methodology • Solution space partitioning: S = S 1 + S 2 + … + S n • Each S k is a tractable optimization problem • min S = min { x 1 , x 2 , … , x n } where x k = min S k • New solution space S’ = { x 1 , x 2 , … , x n } = { S 1 , S 2 , … , S n } • Encoding for { S 1 , S 2 , … , S n } x 1 x 2 9

  10. PLA Folding PLA simple folding multiple folding 10

  11. PLA Folding Solution Space = Row Permutations maximum simple folding matching 11

  12. Array Optimization Row Permutations + Column Permutations + 2D Compactions 12

  13. Array Optimization        Solution Space = , , 13

  14. Floorplan Design Pack modules on a rectangular chip to optimize total area, interconnect cost and other performance measure. Module: – Hard modules B – Soft modules A Connectivity: C D 10 A C 1 5 2 B D 14

  15. Algorithm * + + 6 7 1 1 + * * 5 7 6 5 4 2 3 2 3 4 Slicing Tree Slicing Floorplan 2 3 * 1 + 4 5 + 6 7 * + * Polish Expression 15

  16. Algorithm 16

  17. Algorithm 17

  18. How good are slicing floorplans? 18

  19. Results for Soft Blocks Experimental results => slicing is good for soft modules No. of Circuit runtime(s) deadspace(%) Modules apte 9 0.31 0.74 xerox 10 0.38 0 hp 11 0.45 0 ami33 33 3.22 0.01 ami49 49 6.93 0.13 * all modules have aspect ratio between 0.5 and 2 19

  20. Results for Hard Blocks 13 5 49 1 48 19 36 27 8 6 3 34 16 21 39 31 • Excellent results by slicing 10 44 26 for the largest MCNC 17 30 4 benchmarks ( Cheng, Deng, 41 15 33 22 14 Wong, ASPDAC 2005 ) 32 47 25 11 37 7 29 42 9 38 43 35 28 46 18 23 45 2 24 12 40 20 20

  21. Results on Large Benchmarks • Yan and Chu, DAC ‐ 2008 • Slicing approach produced best results on GSRC & HB large benchmarks 21

  22. Theoretical Analysis Theorem [ Young and Wong ISPD ‐ 97 ] Given a set of soft blocks of total area A total , maximum area A max and shape flexibility r  2 , there exists a slicing floorplan F of these blocks such that:   1 5       area ( F ) min ( 1 ), , ( 1 ) A total   4 r 2 A max   where rA total 22

  23. Can we do better? Conjecture: For each non ‐ slicing floorplan, there exists a slicing floorplan with “similar” area and topology. Are slicing floorplans dense ? slicing floorplan 23

  24. Wheel Floorplans with Squared Blocks Lemma Given any wheel floorplan with 5 squared blocks, there is a “neighboring” slicing floorplan with equal/smaller area. • It is not possible that x1 > x2 and x2 > x3 and x3 > x4 and x4 > x1. Otherwise, x1 > x1! • We may assume x1 ≤ x2. It is easy to see that there is a “neighboring” slicing floorplan which is smaller! 24

  25. Tightly Packed Wheel Floorplans • Tightly packed wheel floorplans – 5 blocks: A, B, C and D identical, E is a square – 0< x ≤ 1; block aspect ratio ∈ [1/2, 2] • Neighboring slicing floorplan – A, B and E: aspect ratio = 2 25

  26. Tightly Packed Wheel Floorplans      1 x 2    2 x x Area Increase =   2 2     2 1 x x   4   2 4(1 x ) x • Area increase is 0% when x = 0.783 • Max area increase is 1.77% when x = 0.328 26

  27. Tightly Packed Wheel Floorplans • When 0.783 ≤ x ≤ 1 – The slicing floorplan can be packed with zero dead ‐ space – Adjust aspect ratios of A, B, C and D – Aspect ratio of E is 2 27

  28. Tightly Packed Wheel Floorplans 2    1 x 2    x  4  R = aspect ratio of A & B = 2 x  1 x R ∈ [1.5625,2] when x ∈ [0.783,1] 28

  29. Tightly Packed Wheel Floorplans  1 x S = aspect ratio of C &D = 2 2 x S ∈ [1,1.455] when x ∈ [0.783, 1] 29

  30. Conclusion • Solution space partitioning: S = S1 + S2 + … + Sn • New solution space S’ = { x1 , x2 , … , xn } = { S1 , S2 , … , Sn } • Encoding for { S1 , S2 , … , Sn } • Significant reduction in solution space size • Keep optimal solutions 30

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend


More recommend