OF DC-I SOLATED G ATE D RIVERS Alon Blumenfeld, Alon Cervera, and - - PowerPoint PPT Presentation

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OF DC-I SOLATED G ATE D RIVERS Alon Blumenfeld, Alon Cervera, and - - PowerPoint PPT Presentation

Oct 01, 2023 15 likes •220 views

A NALYSIS AND D ESIGN OF DC-I SOLATED G ATE D RIVERS Alon Blumenfeld, Alon Cervera, and Shmuel (Sam) Ben-Yaakov Power Electronics Laboratory Department of Electrical and Computer Engineering Ben-Gurion University of the Negev 1 Ben-Gurion

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SLIDE 1

Ben-Gurion University of the Negev – Power Electronics Laboratory

ANALYSIS AND DESIGN

OF DC-ISOLATED GATE DRIVERS

Alon Blumenfeld, Alon Cervera, and Shmuel (Sam) Ben-Yaakov Power Electronics Laboratory Department of Electrical and Computer Engineering Ben-Gurion University of the Negev

November 12 1

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SLIDE 2

Ben-Gurion University of the Negev – Power Electronics Laboratory

Motivation - Existing Solutions

  • 1. Transformer
  • 2. Opto-Coupler
  • 3. Floating power drivers

November 12 2

Drive Cs + Cs +

Vfloat Drive

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SLIDE 3

Ben-Gurion University of the Negev – Power Electronics Laboratory

Motivation

  • Shading differences have

a major impact on serially connected PVs

  • Panels with different light

exposures connected in series can’t all be in MPP

50 100 150 200 250 300 350 400 450 20 40 60 80

3 Serial Connected PVs With Bypass Diodes

𝑊𝑀 [𝑊] 𝑄𝑀 [w]

A PV Panel’s I-V characteristics for various Insolation levels November 12 3

150W

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SLIDE 4

Ben-Gurion University of the Negev – Power Electronics Laboratory

Motivation

  • A voltage equalization method was examined offering

a suitable solution for the shading problem

November 12 4

60% 80% 100% 0.25 0.5 0.75 1 95% 66% 97%

With EQSCC η

Irradiance Ratio

65% 78%

Theoretical and experimental efficiency curves for 2 panels,

  • ne with irradiation swept from 0% to 100%

The EQSCC

EQSCC PV1 PV2 ID Csw IL IO IS IL ID ID

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SLIDE 5

Ben-Gurion University of the Negev – Power Electronics Laboratory

The Problem

  • SCC based equalization system demanded

a technique for driving floating source transistors

  • This demand lead to investigate an alternative coupling

methods at a DC-voltage reference MOSFETs

November 12 5 Vg t

ON OFF

VBUS Vgs t

ON OFF EQSCC PV1 PV2 ID Csw IL IO IS IL ID ID

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SLIDE 6

Ben-Gurion University of the Negev – Power Electronics Laboratory

  • Drive isolation while using DC restoration is a well

known method

  • This work explores the characteristics and problems
  • f the DC restoration solution without using

a transformer

DC-Isolation – The concept

November 12 6

Drive Cs + Cs +

Drive Cs +

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SLIDE 7

Ben-Gurion University of the Negev – Power Electronics Laboratory

  • The DC restoration is practical when the source is

connected to a stable DC voltage

  • The diode restores the needed

DC by clamping the gate to the source during ‘off’ times

DC-Isolation – The concept

November 12 7

EQSCC PV1 PV2 ID Csw IL IO IS IL ID ID

Drive Cs +

PMOS S

Drive Cs +

NMOS S

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SLIDE 8

Ben-Gurion University of the Negev – Power Electronics Laboratory

Basic Implementation

  • 1. Bleeder resistor, allows CS voltage to follow changes in VBUS
  • 2. Series gate resistor, damps the drive circuit
  • 3. Cloop capacitor, minimizes the ground loop impedance

November 12 8

Cloop VBUS Lstray Cs D Rbleed Rs PMOS D G S VCs=VBUS-VDRIVE Drive Cs D Rbleed Rs VBUS NMOS Cloop D G S Lstray VCs=VBUS Drive

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SLIDE 9

Ben-Gurion University of the Negev – Power Electronics Laboratory

Current path

  • During ON:
  • During OFF:

November 12 9

Cs D Rbleed Rs BUS NMOS On Cloop Cs D Rbleed Rs BUS NMOS Off Cloop

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SLIDE 10

Ben-Gurion University of the Negev – Power Electronics Laboratory

Current path

  • During transients in VBUS:

November 12 10

VBUS VBUS increase Cs D Rbleed Rs NMOS Drive Cloop D G S Lstray VBUS VBUS decrease Cs D Rbleed Rs NMOS Drive Cloop D G S Lstray

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SLIDE 11

Ben-Gurion University of the Negev – Power Electronics Laboratory

Design Considerations – DC-Restorer

  • CS – Chosen according to the maximum allowable voltage

ripple:

𝐷𝑡 ≥ 𝑅𝑕𝑏𝑢𝑓 Δ𝑊

𝐷𝑇

  • Cloop - Chosen according a maximum allowed 𝛦𝑊

𝐷𝑚𝑝𝑝𝑞 ripple:

𝐷𝑚𝑝𝑝𝑞 ≥ 𝑅𝑕𝑏𝑢𝑓 Δ𝑊

𝐷𝑚𝑝𝑝𝑞

  • Rbleed – Designed to allow CS follow transients in VBUS, yet

not discharge during ‘on’ periods:

𝑈𝑢𝑠𝑏𝑜𝑡𝑗𝑓𝑜𝑢 > 𝑆𝑐𝑚𝑓𝑓𝑒𝐷𝑇 ≫ 0.5𝑈

𝑇

November 12 11

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SLIDE 12

Ben-Gurion University of the Negev – Power Electronics Laboratory

Design Considerations – DC-Restorer

  • RS – Selected such that the drive circuit’s harmonic quality

factor value will be smaller than 0.5:

𝑆𝑡 ≪ 𝑈

𝑡𝑊 𝑕𝑡

2𝑅𝑕 𝑆𝑡 > 2 ⋅ 𝑀 𝐷𝑡

  • Ploss – Can be estimated according to supply voltage,

switching frequency and the gate charge: 𝑄𝑚𝑝𝑡𝑡 = 𝑊

𝑡𝑣𝑞𝑞𝑚𝑧𝑅𝑕𝑔

November 12 12

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SLIDE 13

Ben-Gurion University of the Negev – Power Electronics Laboratory

Simulations

Measurement of VGS ,with and without Cloop

  • Extra offset occurs in VGS

preventing the ‘off’ levels from reaching zero

  • The diode charges Cs so

that Vgs>-0.7

  • Negative overshoots cause

excess charge on Cs

November 12 13

Without Cloop With Cloop 5.815 5.82 5.825 5.83 5.835 Time (ms) Vgs (PMOS) Vgs (NMOS) 5 10 15

  • 5
  • 10
  • 15

Without Cloop With Cloop

VBUS Rbleed 1.5kΩ Rs 3.3Ω Cgs 5nF CS 470nF Lstray 100nH Cloop 4.7µF 0.05Ω Vtransient Drive Rbleed 1.5kΩ Rs 3.3Ω Cgs 5nF CS 470nF

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SLIDE 14

Ben-Gurion University of the Negev – Power Electronics Laboratory

Simulations

Recovery from transients in VBUS

  • VBUS falls: CS discharges through Rbleed
  • VBUS rises:

– CS charges rapidly through D – Excess charge due to stray inductance is slowly discharged through Rbleed

November 12 14

VBUS Rbleed 1.5kΩ Rs 3.3Ω Cgs 5nF CS 470nF Lstray 100nH Cloop 4.7µF 0.05Ω Vtransient Drive Rbleed 1.5kΩ Rs 3.3Ω Cgs 5nF CS 470nF

49.5 5.0 5.1 5.2

VBUS

5

Vgs (NMOS)

Time (ms)

  • 5
  • 10
  • 15

Vgs (PMOS)

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SLIDE 15

Ben-Gurion University of the Negev – Power Electronics Laboratory

Experimental Study

  • Drivers:

Inverting low side MIC4426 drivers

  • SCC:

flying capacitor

  • DC Restorers:

Passive components

November 12 15

Cloop (C7-C10) were connected close to the source and the driver GND

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SLIDE 16

Ben-Gurion University of the Negev – Power Electronics Laboratory

Experimental Study

  • Voltage equalization

system based SCC

November 12 16

EQSCC PV1 PV2 ID Csw IL IO IS IL ID ID

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SLIDE 17

Ben-Gurion University of the Negev – Power Electronics Laboratory

  • CH1: VgQ1 (N-MOS)
  • CH2: VgQ2 (P-MOS)
  • CH3: VgQ3 (N-MOS)
  • CH4: VgQ4 (P-MOS)
  • D4: U2-OUTB
  • D4: U2-OUTA
  • D4: U1-OUTB
  • D4: U1-OUTA

Experimental Results

November 12 17

VBUS≈22v OFF OFF OFF OFF ON ON ON ON

CGD

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SLIDE 18

Ben-Gurion University of the Negev – Power Electronics Laboratory

Conclusions

  • Simple low-side drivers can properly drive floating

DC referred MOSFETs

  • The method could be adapted for any DC referred

MOSFET by suitable passive circuitry design

  • The proposed solution may help in reducing costs

without penalties in efficiency

November 12 18

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SLIDE 19

Ben-Gurion University of the Negev – Power Electronics Laboratory

Thank You for Your Attention!

November 12 19

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SLIDE 20

Ben-Gurion University of the Negev – Power Electronics Laboratory

Appendix – Half-bridge driver

  • Most H-B drivers use a bootstrap

capacitor - Cb

  • High-side operation relies on that

switch’s source reaching ground potential for Cb to charge

  • The two upper switches in our case

can not be operated by this method

November 12 20

EQSCC PV1 PV2 ID Csw IL IO IS IL ID ID