[PPT] - MSP430 eZ430-rf2500 Guillaume Salagnac November 29, 2011 1 PowerPoint Presentation

SLIDE 1

MSP430 eZ430-rf2500

Guillaume Salagnac November 29, 2011

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SLIDE 2

Embedded Systems

Wikipedia

An embedded system is a computer system designed for specific control functions within a larger system, often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts.

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SLIDE 3

Consumer Electronics

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SLIDE 4

ez430-RF2500

SLAU227A.pdf p.2

Figure 1. eZ430-RF2500

MSP430F2274 18 Accessible Pins Chip Antenna CC2500 2x LEDs Pushbutton USB Powered Spy Bi-Wire & MSP430 Appliation UART 4

SLIDE 5

ez430-RF2500

SLAU227A.pdf p.3

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SLIDE 6

Low-power Operation

Power Time 1mW 0.1µW

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SLIDE 7

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

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SLIDE 8

Target board schematics

SLAU227A.pdf p.16

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SLIDE 9

Target board PCB layout

SLAU227A.pdf p.17

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SLIDE 10

Debugger board schematics

SLAU227A.pdf p.14

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SLIDE 11

Debugger board schematics

SLAU227A.pdf p.15

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SLIDE 12

MSP430F2274 device pinout

SLAS504B.pdf p.5

1 DVSS P1.5/TA0/TMS P1.0/TACLK /ADC 10CLK P1.1/TA 0 P1.2/TA1 P1.3/TA2 P1.4/SMCLK/TCK 13 P2.4/TA 2/A4/VREF+/VeREF+/OA1I0 P2.5/Rosc DVCC TEST/SBWTCK P1.6/TA1/TDI/TCLK 2 3 4 5 6 7 8 10 9 12 14 15 16 17 18 19 30 29 28 27 26 25 24 23 21 22 38 39 37 36 35 34 33 32 XOUT /P2.7 XIN /P2.6 DVSS RST/NMI/SBWTDIO P2.0/ACLK /A0/OA 0I0 P2.1/TAINCLK /SMCLK /A1/OA0O P2.2/TA 0/A2/OA 0I1 P3.0/UCB 0STE /UCA 0CLK /A5 P3.1/UCB 0SIMO /UCB 0SDA DVCC P1.7/TA2/TDO/TDI P2.3/TA 1/A3/VREF− /VeREF− /OA1I1/OA1O P3.7/A7/OA1I2 P3.6/A6/OA0I2 P3.5/UCA 0RXD /UCA 0SOMI P3.4/UCA 0TXD /UCA 0SIMO AVCC AVSS P3.2/UCB0SOMI/UCB0SCL P3.3/UCB0CLK/UCA0STE P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O P4.5/TB2/A14/OA0I3 P4.6/TBOUTH/A15/OA1I3 P4.7/TBCLK

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SLIDE 13

MSP430F2274 Functional Block Diagram

SLAS504B.pdf p.6

Basic Clock System+ RAM 1kB 512B 512B Brownout Protection RST/NMI VCC VSS MCLK SMCLK Watchdog WDT+ 15/16− Bit Timer_A3 3 CC Registers 16MHz CPU

incl. 16

Registers Emulation (2BP) XOUT JTAG Interface Flash 32kB 16kB 8kB ACLK XIN MDB MAB Spy− Bi Wire Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C OA0, OA1 2 Op Amps ADC10 10− Bit 12 Channels, Autoscan, DTC Ports P1/P2 2x8 I/O Interrupt capability, pull− up/down resistors Ports P3/P4 2x8 I/O pull− up/down resistors P1.x/P2.x 2x8 P3.x/P4.x 2x8

NOTE: See port schematics section for detailed I/O information.

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SLIDE 14

MSP430 16-bit Memory Map

SLAU144D.pdf p.1-4

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SLIDE 15

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

Basic Clock System+ RAM 1kB 512B 512B Brownout Protection RST/NMI VCC VSS MCLK SMCLK Watchdog WDT+ 15/16− Bit Timer_A3 3 CC Registers 16MHz CPU

incl. 16

Registers Emulation (2BP) XOUT JTAG Interface Flash 32kB 16kB 8kB ACLK XIN MDB MAB Spy− Bi Wire Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C OA0, OA1 2 Op Amps ADC10 10− Bit 12 Channels, Autoscan, DTC Ports P1/P2 2x8 I/O Interrupt capability, pull− up/down resistors Ports P3/P4 2x8 I/O pull− up/down resistors P1.x/P2.x 2x8 P3.x/P4.x 2x8

NOTE: See port schematics section for detailed I/O information.

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SLIDE 16

GPIO Port Registers

P1DIR: direction, 0=in, 1=out P1OUT: set output P1IN: read input

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SLIDE 17

Example

char P5OUT = (char) 0x0042; *P5OUT = 0x13; volatile unsigned char P5OUT = asm("0x0042"); P5OUT = 0x13; #include <io.h> P5OUT = 0x13;

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SLIDE 18

GPIO Port Schematics Example

(from another MSP430)

port P3, P3.1, input/output with Schmitt−trigger

P3.1/SIMO0 P3IN.1 Pad Logic EN D P3OUT1 P3DIR.1 P3SEL.1 (SI)MO0 1 1 DCM_SIMO SYNC MM STE STC From USART0 SI(MO)0 To USART0 0: Input 1: Output

P3SEL: 0=GPIO, 1=another peripheral

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SLIDE 19

Pin Sharing

SLAS504B.pdf p.9

Terminal Functions, MSP430x22x4

TERMINAL NAME DA RHA I/O DESCRIPTION NAME NO. NO. I/O DESCRIPTION P1.0/TACLK/ ADC10CLK 31 29 I/O General-purpose digital I/O pin Timer_A, clock signal TACLK input ADC10, conversion clock P1.1/TA0 32 30 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit P1.2/TA1 33 31 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/TA2 34 32 I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/SMCLK/ TCK 35 33 I/O General-purpose digital I/O pin / SMCLK signal output Test Clock input for device programming and test P1.5/TA0/ TMS 36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output Test Mode Select input for device programming and test P1.6/TA1/ TDI/TCLK 37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output Test Data Input or Test Clock Input for programming and test P1.7/TA2/ TDO/TDI† 38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output Test Data Output or Test Data Input for programming and test P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK output ADC10, analog input A0 / OA0, analog input I0 P2.1/TAINCLK/SMCLK/ A1/OA0O 9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK SMCLK signal output ADC10, analog input A1 / OA0, analog output P2.2/TA0/ A2/OA0I1 10 8 I/O General-purpose digital I/O pin Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 / OA0, analog input I1 P2.3/TA1/ A3/VREF−/VeREF− /OA1I1/OA1O 29 27 I/O General-purpose digital I/O pin Timer_A, capture CCI1B input, compare: OUT1 output ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1 / OA1, analog output P2.4/TA2/ 30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output

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SLIDE 20

GPIO Port Schematics Example

(from another MSP430)

input/output schematic

port P1, P1.0 to P1.7, input/output with Schmitt−trigger

P1.0/T ACLK .. P1IN.x Module X IN Pad Logic Interrupt Flag Edge Select Interrupt P1SEL.x P1IES.x P1IFG.x P1IE.x P1IRQ.x EN D Set EN Q P1OUT .x P1DIR.x P1SEL.x Module X OUT Direction Control From Module 1 1 P1.7/T A2

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SLIDE 21

GPIO Example

#include <io.h> #define BIT_GREEN (1 << 1) #define BIT_RED (1 << 0) void wait(unsigned int n) { int i; for(i=0;i<n;i++) { asm(" nop;"); asm(" nop;"); } } int main(void) { unsigned char b; P1DIR |= (BIT_GREEN | BIT_RED); P1SEL &= ~(BIT_GREEN | BIT_RED); P1OUT &= ~(BIT_GREEN | BIT_RED); b = 0x01; while (1) { wait(50000); wait(50000); wait(50000); wait(50000); P1OUT = b; b <<= 1; if (b == 0x4) b = 0x01; } return 0; }

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SLIDE 22

Bitwise Operators in C

...illustrated with non-C syntax

A = 0b01101001 ~A = 0b10010110 A<<2 = 0b10100100 A<<2 = 0b00011010 A|= 0b00000010 => A=0b01101011 A&=~0b00001000 => A=0b01100001 A^= 0b10001000 => A=0b11100001

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SLIDE 23

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

Basic Clock System+ RAM 1kB 512B 512B Brownout Protection RST/NMI VCC VSS MCLK SMCLK Watchdog WDT+ 15/16− Bit Timer_A3 3 CC Registers 16MHz CPU

incl. 16

Registers Emulation (2BP) XOUT JTAG Interface Flash 32kB 16kB 8kB ACLK XIN MDB MAB Spy− Bi Wire Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C OA0, OA1 2 Op Amps ADC10 10− Bit 12 Channels, Autoscan, DTC Ports P1/P2 2x8 I/O Interrupt capability, pull− up/down resistors Ports P3/P4 2x8 I/O pull− up/down resistors P1.x/P2.x 2x8 P3.x/P4.x 2x8

NOTE: See port schematics section for detailed I/O information.

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SLIDE 24

Interrupts

An interrupt can only occur when both bit General Interrupt Enable (GIE) set in status register Interrupt Enable bit set in specific peripheral register

e.g. PxIE in ports 1 and 2

Acknowledgement is implicit for single-source interrupts necessary for multiple-source interrupts

e.g. PxIFG in port 1 and 2

Interrupt nesting is disabled by default GIE is cleared upon entering ISR

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SLIDE 25

ISR Example

using GCC intrisincs

interrupt (PORT1_VECTOR) PORT1_ISR(void) { if (P1IFG & (P1IE & (1<<2) )) { SWITCH_RED_LED(); } P1IFG=0; }

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SLIDE 26

MSP430 16-bit Memory Map

SLAU144D.pdf p.1-4

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SLIDE 27

MSP430F2274 Peripherals mapping

SLAS504B.pdf p.22

PERIPHERALS WITH BYTE ACCESS (continued) Basic Clock System+ Basic clock system control 3 Basic clock system control 2 Basic clock system control 1 DCO clock frequency control BCSCTL3 BCSCTL2 BCSCTL1 DCOCTL 053h 058h 057h 056h Port P4 Port P4 resistor enable Port P4 selection Port P4 direction Port P4 output Port P4 input P4REN P4SEL P4DIR P4OUT P4IN 011h 01Fh 01Eh 01Dh 01Ch Port P3 Port P3 resistor enable Port P3 selection Port P3 direction Port P3 output Port P3 input P3REN P3SEL P3DIR P3OUT P3IN 010h 01Bh 01Ah 019h 018h Port P2 Port P2 resistor enable Port P2 selection Port P2 interrupt enable Port P2 interrupt edge select Port P2 interrupt flag Port P2 direction Port P2 output Port P2 input P2REN P2SEL P2IE P2IES P2IFG P2DIR P2OUT P2IN 02Fh 02Eh 02Dh 02Ch 02Bh 02Ah 029h 028h Port P1 Port P1 resistor enable Port P1 selection Port P1 interrupt enable Port P1 interrupt edge select Port P1 interrupt flag Port P1 direction Port P1 output Port P1 input P1REN P1SEL P1IE P1IES P1IFG P1DIR P1OUT P1IN 027h 026h 025h 024h 023h 022h 021h 020h Special Function SFR interrupt flag 2 SFR interrupt flag 1 SFR interrupt enable 2 SFR interrupt enable 1 IFG2 IFG1 IE2 IE1 003h 002h 001h 000h

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SLIDE 28

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

Basic Clock System+ RAM 1kB 512B 512B Brownout Protection RST/NMI VCC VSS MCLK SMCLK Watchdog WDT+ 15/16− Bit Timer_A3 3 CC Registers 16MHz CPU

incl. 16

Registers Emulation (2BP) XOUT JTAG Interface Flash 32kB 16kB 8kB ACLK XIN MDB MAB Spy− Bi Wire Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C OA0, OA1 2 Op Amps ADC10 10− Bit 12 Channels, Autoscan, DTC Ports P1/P2 2x8 I/O Interrupt capability, pull− up/down resistors Ports P3/P4 2x8 I/O pull− up/down resistors P1.x/P2.x 2x8 P3.x/P4.x 2x8

NOTE: See port schematics section for detailed I/O information.

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SLIDE 29

Oscillators and clocks

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SLIDE 30

Basic Clock Module

SLAU144D.pdf p.5-3

$%&%'() *+*,*-*. $/012 !"#$ 345677 879:+38; $3638; 9/< 965: $%&%'() *+*,*-*. $/0=2 %!"#$ >3?+ $/0>2 &"#$ =@%A >BCD(E 3FGHI 1J2%FF@)B 3FGHI >JK >BCD(E 3FGHI $36 $362 $3 ?(A()@DG) >3?L M>N82 GOO >N8> + L >N8=2 LL L+ +L ++ + L + L $%&%'() *+*,*-*. =G'JF@DG) + L A AP+ 9:> 93142 879:+ 6CH%FF@DG) 87 L 0 876OO L 0 =%AQ 4JFC 7%FD() 879:+>2 =6$2 (FC( +L =%AQ 4JFC( 7%FD() /AD()A@F 84*87 08638; 9:,/< 9:,65: 9:,677 9: =%AQ 4JFC( 7%FD() 3GAA(HD(' GAFB RS(A 9:, AGD T)(C(AD GA" "HS%T 9:,> 033 + L $36M 6CH%FF@DG)U 9:+6OO 9:, 6CH%FF@DG)U MGCHU 6>3677 9:U

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SLIDE 31

Digitally-Controlled Oscillator

SLAU144D.pdf p.5-7

./013R

./01 3 Q! 6,73R 6,73# 6,73V 6,73Q 6,73K 6,738 6,73! 6,73W %6,7 KRRRR XYZ QRR XYZ QRRR XYZ ./01 3 # 31

SLIDE 32

Sleep modes

SLAU144D.pdf p.2-14

+#G H( +,, !I, !!G #F, #+G ?, $G , J(, J(! J(+ J($ !,, GG +! #I ## ,@? ,@I ,@# ,@# KLL M + K KLL M !@! K N<'8.:065 (74'3 OLLPH .: # (QD

32

SLIDE 33

Timers

A timer is a 16-bit counter which counts cycles from a selectable clock source in a certain way (up, down, continuous) Can be used in two ways : memorize its value on certain events (capture mode)

r

trigger an interrupt when reaching a given value (compare mode) Each timer has two interrupt lines: implicit acknowledgement: TxCCR0 vector

ack. must be done by software: TxIV vector

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SLIDE 34

Timer A

SLAU144D.pdf p.12-3

%&'()*)+&* " %%, !- . %%,/0 1234150 %)(+6*7 4&87 %40 /9:; /%/ %1< =&>?; 16+(6+ 2:?+" 5 /7+ @ A@2. 123 123" /?>:)= B7C7+ DE5 <%% %%,"F %%,"G A@2" 5?H?87* !I"IJIK %&6:+ 4&87 !L# #M?+ 3?'7* 3FB B% F%NO /4%NO 3F%NO ,E%NO /7+ 3F,PD !- . 3F//AN0 4%0 ,50 .. .! !. !! %=7)* 3?'7* %=&;Q A@2. 3?'7* %=&;Q 3?'7* %=&;Q /%%, R F AE !!"# S1B 3F%NB !!"$ %&'() *+,-. .. .! !. !! %FS ! . ! . !!"/ /7+ 3F%%B" %%,PD 3F%%B"

34

SLIDE 35

Timer B

SLAU144D.pdf p.13-3

!!"# $%&'()(*%) + $$, !- . /012/34 $('*5)6 2%76 $24 89:; $/< =%>?; /5*'5* 0:?*+ 3 86* @ A@0. /01 /01+ 8?>:(= B6C6* D/B A@0+ 3?E?76) !FGFHFI $%5:* 2%76 !+# #J?* 1?&6) 1KB 86* 1K,LM !- . 2$4 ,34 $=6() 1K$NB 1?&6) $=%;O !!"$ A@0. 1?&6) $=%;O 1?&6) $=%;O <$$ 1KBP. 0DF3/QR A@0. $NN34 $R1N4 N%(7 !!"% !!"& !!"' !!"( !!") *+,-. /0123 1K$$B+ B$ !. !G !+ I 1K$NMBD4 $$B- $$BH $$B! M)%5' N%(7 N%>?; M)%5' N%(7 N%>?; 1K88AN4 .. .! !. !! MR3 <$$ $$,+S $$,+K .. .! !. !! $$,84 .. .! !. !! .. .! !. !! $SD ! . 8$8 ! . 86* 1K$$B+ $$,LM $%&'()6 N(*;T 1K$N+ S$NU 82$NU 1K$NU

35

SLIDE 36

Timers: Up mode

SLAU144D.pdf p.12-6

4& 45555& %=>>?4

>>?4# #! >>?4 4& %-*'1 >9+6I %-*'1 J'0 %=F5G J'0 %=>>?4 >>F5G !& >>?4# #! >>?4 4& 36

SLIDE 37

Timers: Continuous mode

SLAU144D.pdf p.12-8

DAAAA& %>??@D1 %>??@D2 %>??@D( %>??@D0 +! +D +D %>??@!1 %>??@!2 %>??@!( %>??@!0 +! +! +D

37

SLIDE 38

Timers: Up-down mode

SLAU144D.pdf p.12-10

$&

$JJJJ&

.LJP

Q73@73 R:9' "N -:++2'F0'6'3 Q73@73 R:9' SN -:++2'FH'3

.//0$
.//0!

TUV!

.LJP

L(3'557@3 T='(36 TUV! TUV$ TUV! TUV! TUV$

.//0"

TUV" TUV" TUV" TUV" W'*9 -,4'

38

SLIDE 39

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

Basic Clock System+ RAM 1kB 512B 512B Brownout Protection RST/NMI VCC VSS MCLK SMCLK Watchdog WDT+ 15/16− Bit Timer_A3 3 CC Registers 16MHz CPU

incl. 16

Registers Emulation (2BP) XOUT JTAG Interface Flash 32kB 16kB 8kB ACLK XIN MDB MAB Spy− Bi Wire Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C OA0, OA1 2 Op Amps ADC10 10− Bit 12 Channels, Autoscan, DTC Ports P1/P2 2x8 I/O Interrupt capability, pull− up/down resistors Ports P3/P4 2x8 I/O pull− up/down resistors P1.x/P2.x 2x8 P3.x/P4.x 2x8

NOTE: See port schematics section for detailed I/O information.

39

SLIDE 40

Serial Communication

Examples of serial protocols: Morse code, USB, Firewire, USB, Ethernet, RS232, I2C, SPI... The MSP430F2274 has two UARTs (both interrupt-capable): USCI_A0: UART, I2C, SPI, IrDA USCI_B0: SPI, I2C Asynchronous communication (UART) : Both ends have to agree on the communication protocol: encoding, frame length, reference frequency, ...

40

SLIDE 41

Asynchronous Serial Protocol

SLAU144D.pdf p.15-5

YA436/: J6/. &2AGZ T ![ Y',,3-55 J6/. &2XL\GE T !][ X43C 1D47- \] \^ \_ '\ A' 1A 1A YLD/6+%4? J6/. 2+%,6/6+%[ YR%, 1/+D J6/. &21AJ T ![ Y`/0 \4/4 J6/. &2_J$) T ][ 1)

41

SLIDE 42

USCI Block Diagram: UART Mode

SLAU144D.pdf p.15-4

%&'()*+&,

./0

1%./0 1%./0 22 2! !2 !! 3.114/5 3.2./0 6,789*)7,:;<=<'7, >797<=7 ?*(',*+7 @7A7,*+&, 3.2?>5 !B 3.?>C5 $ 3.?>15 D 3.E1!B 3.>F4>> 4,,&, C)*G8 17+ C)*G8 3.64 3.C4 3.E4 3.-?4H >797<=7 1I<J+ >7G<8+7, >797<=7 ?(JJ7, 3.2>F?3C >797<=7 1+*+7 %*9I<A7 ! 2 3.K>4H 3.64H 3.6-> 3.%1? 3.L?KM 3.;E>% 3.%E;45 N 3.16? 17+ 3.?>0 17+ 3.-;;>:3.K;/4 2 ! 3./K1M4H 3.2>F ! 2 3.K>>F6/ K,;- ;79&'7, 3.K>>FC4 3.K>>FC/5 B M,*A8O<+ ?(JJ7, 3.2MF?3C M,*A8O<+ 1+*+7 %*9I<A7 3.MF-;;> 3.MF?>0 M,*A8O<+ 1I<J+ >7G<8+7, 3.64H 3.6-> 3.%1? 3.L?KM 3.K>4H 3.K>MF6/5 B 2 ! K,;- 4A9&'7, 3.2MF M,*A8O<+ .)&9P >797<=7 .)&9P ?>./0 3.%E;45 N 3.16? 3.>F4K4 3.>F?>0K4 17+ 3.2>FKC@ 17+ 3.2MFKC@ 17+ >FKC@

42

SLIDE 43

USCI Block Diagram: SPI Mode

SLAU144D.pdf p.14-4

%&'( )*&'( )*&'( ++ +! !+ !! ,&))-'. /0% 123456732089:9;32 <9= &7>5? @3A326=>2 ,&.<B. !" B3539:3 )C9D= B3E94=32 B3539:3 <FDD32 ,&.BG<,H B3539:3 )=6=3 *65C9A3 ,&*)< ,&I<JK ! + ,&*)K ,&.)L*J K26A4M9= <FDD32 ,&.KG<,H K26A4M9= )=6=3 *65C9A3 K26A4M9= )C9D= B3E94=32 ,&*)< ,&I<JK <B&'( )3= ,&.BGJH@ )3= ,&.KGJH@ + ! ,&'J)K-/ &7>5? 89235=9>AN 1C643 6A; 1>7629=O ,&&(1P ,&&(1' ,&.)J*L ,&.&'( )3= ,&L- K26A4M9= -A6Q73 &>A=2>7 R ,&*L8-. ,&.)K- )3= ,&H-

43

SLIDE 44

USCI Block Diagram: I2C Mode

SLAU144D.pdf p.17-4

%&'( )*&'( )*&'( ++ +! !+ !! ,&))-'. ,&!&'( /0123451067898:10 ;8< &5=3> ?1@104<=0 ,&.;A. !B ;A&'( )5491 %::0122 ,&!)% C04@2D8< )E8F< A1G82<10 ,&*)C C04@2D8< ;HFF10 ,&!CI;,J KL& )<4<1 *43E8@1 MN@ %::0122 ,&!M% A131891 )E8F< A1G82<10 ,&%!+ A131891 ;HFF10 ,&!AI;,J ,&?&-O ,&.)7% ,&.)&' ,&)'%!+

44

SLIDE 45

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

Basic Clock System+ RAM 1kB 512B 512B Brownout Protection RST/NMI VCC VSS MCLK SMCLK Watchdog WDT+ 15/16− Bit Timer_A3 3 CC Registers 16MHz CPU

incl. 16

Registers Emulation (2BP) XOUT JTAG Interface Flash 32kB 16kB 8kB ACLK XIN MDB MAB Spy− Bi Wire Timer_B3 3 CC Registers, Shadow Reg USCI_A0: UART/LIN, IrDA, SPI USCI_B0: SPI, I2C OA0, OA1 2 Op Amps ADC10 10− Bit 12 Channels, Autoscan, DTC Ports P1/P2 2x8 I/O Interrupt capability, pull− up/down resistors Ports P3/P4 2x8 I/O pull− up/down resistors P1.x/P2.x 2x8 P3.x/P4.x 2x8

NOTE: See port schematics section for detailed I/O information.

45

SLIDE 46

ADC10

%&'()* &+,

.),

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46

SLIDE 47

Conclusion: MSP430 eZ430-rf2500

Development platform cheap very limited resources Microcontroller architecture all peripherals are memory-mapped low-power modes Not presented: CC2500 Radio Module wireless communication

47

MSP430 eZ430-rf2500

Guillaume Salagnac November 29, 2011

Embedded Systems

Wikipedia

An embedded system is a computer system designed for specific control functions within a larger system, often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts.

Consumer Electronics

ez430-RF2500

SLAU227A.pdf p.2

ez430-RF2500

SLAU227A.pdf p.3

Low-power Operation

Power Time 1mW 0.1µW

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

Target board schematics

SLAU227A.pdf p.16

Target board PCB layout

SLAU227A.pdf p.17

Debugger board schematics

SLAU227A.pdf p.14

Debugger board schematics

SLAU227A.pdf p.15

MSP430F2274 device pinout

SLAS504B.pdf p.5

MSP430F2274 Functional Block Diagram

SLAS504B.pdf p.6

MSP430 16-bit Memory Map

SLAU144D.pdf p.1-4

Outline

1

Introduction

2

Schematics and Pinout

3

Internal structure

4

Digital Input/Output

5

Interrupts

6

Managing time

7

Serial Communication

8

Analog Input/Output

9

Conclusion

GPIO Port Registers

P1DIR: direction, 0=in, 1=out P1OUT: set output P1IN: read input

Example

char *P5OUT = (char*) 0x0042; *P5OUT = 0x13; volatile unsigned char P5OUT = asm("0x0042"); P5OUT = 0x13; #include <io.h> P5OUT = 0x13;

GPIO Port Schematics Example

(from another MSP430)

P3SEL: 0=GPIO, 1=another peripheral

Pin Sharing

SLAS504B.pdf p.9

GPIO Port Schematics Example

(from another MSP430)

GPIO Example

Bitwise Operators in C

...illustrated with non-C syntax

A = 0b01101001 ~A = 0b10010110 A<<2 = 0b10100100 A<<2 = 0b00011010 A|= 0b00000010 => A=0b01101011 A&=~0b00001000 => A=0b01100001 A^= 0b10001000 => A=0b11100001

Outline

char P5OUT = (char) 0x0042; *P5OUT = 0x13; volatile unsigned char P5OUT = asm("0x0042"); P5OUT = 0x13; #include <io.h> P5OUT = 0x13;

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