MSP430 eZ430-rf2500 Guillaume Salagnac November 29, 2011 1 - PowerPoint PPT Presentation

MSP430 eZ430-rf2500 Guillaume Salagnac November 29, 2011 1

Embedded Systems Wikipedia An embedded system is a computer system designed for specific control functions within a larger system, often with real-time computing constraints. It is embedded as part of a complete device often including hardware and mechanical parts. 2

Consumer Electronics 3

ez430-RF2500 SLAU227A.pdf p.2 Spy Bi-Wire & 2x LEDs Pushbutton MSP430 Appliation UART CC2500 Chip Antenna USB Powered MSP430F2274 18 Accessible Pins Figure 1. eZ430-RF2500 4

ez430-RF2500 SLAU227A.pdf p.3 5

Low-power Operation Power 1mW 0.1 µ W Time 6

Outline Introduction 1 Schematics and Pinout 2 Internal structure 3 Digital Input/Output 4 Interrupts 5 Managing time 6 Serial Communication 7 Analog Input/Output 8 Conclusion 9 7

8 SLAU227A.pdf p.16 Target board schematics

Target board PCB layout SLAU227A.pdf p.17 9

10 SLAU227A.pdf p.14 Debugger board schematics

11 SLAU227A.pdf p.15 Debugger board schematics

MSP430F2274 device pinout SLAS504B.pdf p.5 P1.6/TA1/TDI/TCLK P1.7/TA2/TDO/TDI P1.4/SMCLK/TCK TEST/SBWTCK P1.5/TA0/TMS P2.5/Rosc P1.3/TA2 P1.2/TA1 DVCC DVCC 39 38 37 36 35 34 33 32 DVSS 1 30 P1.1/TA 0 XOUT /P2.7 2 29 P1.0/TACLK /ADC 10CLK XIN /P2.6 3 28 P2.4/TA 2/A4/VREF+/VeREF+/OA1I0 DVSS 4 27 P2.3/TA 1/A3/VREF − /VeREF − /OA1I1/OA1O RST/NMI/SBWTDIO 5 26 P3.7/A7/OA1I2 P2.0/ACLK /A0/OA 0I0 6 25 P3.6/A6/OA0I2 P2.1/TAINCLK /SMCLK /A1/OA0O 7 24 P3.5/UCA 0RXD /UCA 0SOMI P2.2/TA 0/A2/OA 0I1 8 23 P3.4/UCA 0TXD /UCA 0SIMO P3.0/UCB 0STE /UCA 0CLK /A5 9 22 P4.7/TBCLK P3.1/UCB 0SIMO /UCB 0SDA 10 21 P4.6/TBOUTH/A15/OA1I3 12 13 14 15 16 17 18 19 P3.3/UCB0CLK/UCA0STE AVSS AVCC P4.0/TB0 P4.1/TB1 P4.2/TB2 P4.3/TB0/A12/OA0O P4.4/TB1/A13/OA1O P4.5/TB2/A14/OA0I3 P3.2/UCB0SOMI/UCB0SCL 12

MSP430F2274 Functional Block Diagram SLAS504B.pdf p.6 VCC VSS P1.x/P2.x P3.x/P4.x 2x8 2x8 XIN XOUT ADC10 Ports P1/P2 ACLK Flash RAM 10 − Bit Ports P3/P4 Basic Clock OA0, OA1 2x8 I/O System+ SMCLK 32kB 1kB 12 Interrupt 2x8 I/O 16kB 512B Channels, 2 Op Amps capability, pull − up/down 8kB 512B Autoscan, pull − up/down resistors MCLK DTC resistors MAB 16MHz CPU incl. 16 Registers MDB Emulation (2BP) Timer_B3 USCI_A0: Watchdog Timer_A3 UART/LIN, JTAG Brownout WDT+ 3 CC IrDA, SPI Interface Protection 3 CC Registers, USCI_B0: 15/16 − Bit Registers Shadow SPI, I2C Reg Spy − Bi Wire RST/NMI NOTE: See port schematics section for detailed I/O information. 13

MSP430 16-bit Memory Map SLAU144D.pdf p.1-4 14

Outline Introduction 1 Schematics and Pinout 2 VCC VSS P1.x/P2.x P3.x/P4.x 2x8 2x8 Internal structure 3 XIN XOUT ADC10 Ports P1/P2 ACLK Basic Clock Flash RAM 10 − Bit Ports P3/P4 System+ OA0, OA1 2x8 I/O SMCLK 32kB 1kB 12 Interrupt 2x8 I/O 16kB 512B Channels, 2 Op Amps capability, pull − up/down Digital Input/Output 4 MCLK 8kB 512B Autoscan, pull − up/down resistors DTC resistors MAB 16MHz CPU incl. 16 Registers Interrupts MDB 5 Emulation (2BP) Timer_B3 USCI_A0: Watchdog Timer_A3 UART/LIN, JTAG Brownout WDT+ 3 CC IrDA, SPI Managing time Interface Protection 3 CC Registers, 6 USCI_B0: 15/16 − Bit Registers Shadow SPI, I2C Reg Spy − Bi Wire Serial Communication 7 RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output Conclusion 9 15

GPIO Port Registers P1DIR: direction, 0=in, 1=out P1OUT: set output P1IN: read input 16

Example char *P5OUT = ( char *) 0x0042; *P5OUT = 0x13; volatile unsigned char P5OUT = asm("0x0042"); P5OUT = 0x13; #include <io.h> P5OUT = 0x13; 17

GPIO Port Schematics Example (from another MSP430) port P3, P3.1, input/output with Schmitt − trigger P3SEL.1 0: Input 0 1: Output SYNC P3DIR.1 MM 1 DCM_SIMO STC Pad Logic P3.1/SIMO0 STE 0 P3OUT1 (SI)MO0 1 From USART0 P3IN.1 EN SI(MO)0 D To USART0 P3SEL: 0=GPIO, 1=another peripheral 18

Pin Sharing SLAS504B.pdf p.9 Terminal Functions, MSP430x22x4 TERMINAL DA RHA DESCRIPTION DESCRIPTION NAME NAME I/O I/O NO. NO. P1.0/TACLK/ 31 29 I/O General-purpose digital I/O pin ADC10CLK Timer_A, clock signal TACLK input ADC10, conversion clock P1.1/TA0 32 30 I/O General-purpose digital I/O pin Timer_A, capture: CCI0A input, compare: OUT0 output/BSL transmit P1.2/TA1 33 31 I/O General-purpose digital I/O pin Timer_A, capture: CCI1A input, compare: OUT1 output P1.3/TA2 34 32 I/O General-purpose digital I/O pin Timer_A, capture: CCI2A input, compare: OUT2 output P1.4/SMCLK/ 35 33 I/O General-purpose digital I/O pin / SMCLK signal output TCK Test Clock input for device programming and test P1.5/TA0/ 36 34 I/O General-purpose digital I/O pin / Timer_A, compare: OUT0 output TMS Test Mode Select input for device programming and test P1.6/TA1/ 37 35 I/O General-purpose digital I/O pin / Timer_A, compare: OUT1 output TDI/TCLK Test Data Input or Test Clock Input for programming and test P1.7/TA2/ 38 36 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output TDO/TDI † Test Data Output or Test Data Input for programming and test P2.0/ACLK/A0/OA0I0 8 6 I/O General-purpose digital I/O pin / ACLK output ADC10, analog input A0 / OA0, analog input I0 P2.1/TAINCLK/SMCLK/ 9 7 I/O General-purpose digital I/O pin / Timer_A, clock signal at INCLK A1/OA0O SMCLK signal output ADC10, analog input A1 / OA0, analog output P2.2/TA0/ 10 8 I/O General-purpose digital I/O pin A2/OA0I1 Timer_A, capture: CCI0B input/BSL receive, compare: OUT0 output ADC10, analog input A2 / OA0, analog input I1 P2.3/TA1/ 29 27 I/O General-purpose digital I/O pin A3/V REF − /V eREF − Timer_A, capture CCI1B input, compare: OUT1 output /OA1I1/OA1O ADC10, analog input A3 / negative reference voltage output/input OA1, analog input I1 / OA1, analog output P2.4/TA2/ 30 28 I/O General-purpose digital I/O pin / Timer_A, compare: OUT2 output 19

GPIO Port Schematics Example (from another MSP430) input/output schematic port P1, P1.0 to P1.7, input/output with Schmitt − trigger P1SEL.x 0 P1DIR.x Direction Control 1 From Module Pad Logic P1.0/T ACLK .. 0 P1OUT .x Module X OUT 1 P1.7/T A2 P1IN.x EN Module X IN D P1IRQ.x P1IE.x Interrupt EN Edge Q Set P1IFG.x Select Interrupt Flag P1IES.x P1SEL.x 20

GPIO Example int main( void ) { #include <io.h> unsigned char b; P1DIR |= (BIT_GREEN | BIT_RED); #define BIT_GREEN (1 << 1) P1SEL &= ~(BIT_GREEN | BIT_RED); #define BIT_RED (1 << 0) P1OUT &= ~(BIT_GREEN | BIT_RED); b = 0x01; void wait( unsigned int n) while (1) { { int i; wait(50000); wait(50000); for (i=0;i<n;i++) wait(50000); wait(50000); { P1OUT = b; asm(" nop;"); b <<= 1; asm(" nop;"); if (b == 0x4) } b = 0x01; } } return 0; } 21

Bitwise Operators in C ...illustrated with non-C syntax A = 0b01101001 ~A = 0b 10010110 A<<2 = 0b101001 00 A<<2 = 0b 00 011010 A|= 0b00000010 => A=0b011010 1 1 A&=~0b00001000 => A=0b0110 0 001 A^= 0b10001000 => A=0b 1 110 0 001 22

Outline Introduction 1 Schematics and Pinout 2 VCC VSS P1.x/P2.x P3.x/P4.x 2x8 2x8 Internal structure 3 XIN XOUT ADC10 Ports P1/P2 ACLK Basic Clock Flash RAM 10 − Bit Ports P3/P4 System+ OA0, OA1 2x8 I/O SMCLK 32kB 1kB 12 Interrupt 2x8 I/O 16kB 512B Channels, 2 Op Amps capability, pull − up/down Digital Input/Output 4 MCLK 8kB 512B Autoscan, pull − up/down resistors DTC resistors MAB 16MHz CPU incl. 16 Registers Interrupts MDB 5 Emulation (2BP) Timer_B3 USCI_A0: Watchdog Timer_A3 UART/LIN, JTAG Brownout WDT+ 3 CC IrDA, SPI Managing time Interface Protection 3 CC Registers, 6 USCI_B0: 15/16 − Bit Registers Shadow SPI, I2C Reg Spy − Bi Wire Serial Communication 7 RST/NMI NOTE: See port schematics section for detailed I/O information. 8 Analog Input/Output Conclusion 9 23

Interrupts An interrupt can only occur when both bit General Interrupt Enable (GIE) set in status register Interrupt Enable bit set in specific peripheral register e.g. PxIE in ports 1 and 2 Acknowledgement is implicit for single-source interrupts necessary for multiple-source interrupts e.g. PxIFG in port 1 and 2 Interrupt nesting is disabled by default GIE is cleared upon entering ISR 24

ISR Example using GCC intrisincs interrupt (PORT1_VECTOR) PORT1_ISR( void ) { if (P1IFG & (P1IE & (1<<2) )) { SWITCH_RED_LED(); } P1IFG=0; } 25

MSP430 16-bit Memory Map SLAU144D.pdf p.1-4 26