Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX - PowerPoint PPT Presentation

Message scheduling to reduce AFDX jitter in a mixed NoC/AFDX architecture J´ erˆ ome Ermont, Sandrine Mouysset, Jean-Luc Scharbarg and Christian Fraboul Universit´ e de Toulouse - IRIT - INPT/ENSEEIHT October 12, 2018 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 1/15

Context: Avionics architecture of modern planes Avionics computers: Mono-core processors: execute avionics functions following IMA (Integrated Modular Avionics) End Systems: interface between CPU and AFDX AFDX network: Interconnection of several avionics computers VL: unidirectionnal flow between one source ES to one or more destination ES BAG: minimum interval time between 2 frames of a VL J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 2/15

Transmission of VLs by an ES VLs from different partitions share the same ES Scheduler between VLs into the ES Introduces a jitter: delay between the beginning of the BAG and the effective transmission of the frame AFDX constraint: jitter < 500 µ s J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 3/15

Envisioned avionics architecture → To replace mono-core processing unit by many-cores Different applications can be executed in parallel 2 different communications: Intra-NoC communication Inter-NoC communication J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 4/15

Problem Statement BAG of VL1 t1 t2 DDR ETH J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA Command t1 VL1 t2 DDR ETH J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA Command t1 VL1 t2 WCTT DDR ETH DDR ETH VL1 jitter J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA Command t1 VL1 VL2 t2 WCTT DDR ETH DDR ETH VL1 jitter J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA DMA Command Command t1 VL1 VL1 VL2 t2 WCTT DDR ETH DDR ETH VL1 VL2 jitter J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA DMA Command Command t1 VL1 VL1 VL2 t2 WCTT DDR WCTT DDR ETH ETH DDR ETH VL1 VL2 jitter J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA DMA Command Command t1 VL1 VL1 VL2 t2 WCTT DDR WCTT DDR WCTT DDR ETH ETH ETH DDR ETH VL1 VL2 VL1 jitter jitter The jitter depends on the WCTT of flows from other applications WCTT depends on the blocking mechanism of the NoC J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

Problem Statement BAG of VL1 DMA DMA Command Command t1 VL1 VL1 VL2 t2 WCTT DDR WCTT DDR WCTT DDR ETH ETH ETH DDR ETH VL1 VL2 VL1 jitter jitter The jitter depends on the WCTT of flows from other applications WCTT depends on the blocking mechanism of the NoC Problem How to reduce the jitter induced by the transmission on the NoC ? J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 5/15

A first solution: minimizing the contention for other applications Minimizing contentions reduces the maximum jitter A new application mapping: Extended Map IO [1] port18 port17 port16 port15 port14 port13 port12 port11 th3 th5 th15 tf11 tf10 tf7 tf5 tf2 tf0 tf1 10 FADEC13 th13 th12 th14 tf4 tf3 tf12 tf9 tf8 tf6 9 FADEC7 th11 th10 th2 th9 th3 th2 th1 th0 tf6 tf2 8 th6 th7 th8 th1 th4 th9 th8 th5 tf4 tf1 7 HM10 th7 th6 th0 HM9 HM7 tf5 tf0 th1 th6 th0 th4 th0 6 HM16 th4 th9 th0 th3 th2 th7 tf3 (0,5) But not for all configurations th1 th5 5 FADEC11 th6 th4 th3 th1 th5 th4 th2 th8 tf7 tf5 4 HM11 th5 th10 tf8 th6 th4 th5 th3 t DDR tf4 th6 3 th8 th7 th11 th7 th8 tf10tf9 tf6 th9 2 th2 th3 th10 th2 th1 th0 tf0 tf1 tf2 tf3 HM12 1 port8 port7 port6 port5 port4 port3 port2 port1 (0,0) (10,0) 0 10 9 8 7 6 5 4 3 2 1 0 [1] Towards a mixed NoC/AFDX architecture for avionics applications, Laure Abdallah and al. , WFCS 2017 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 6/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . 0 APP4 APP2 . 1 APP1 APP3 . 2 WCTT of VL1 . 3 APP1 . 4 APP2 . 5 APP1 APP3 . 6 . 7 APP1 . 8 APP2 . 9 APP1 APP3 . 10 . 11 APP1 . 12 APP2 . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . 0 APP4 APP2 . 1 APP1 APP3 . 2 WCTT of VL1 . 3 APP1 . 4 APP2 . 5 APP1 APP3 . 6 . 7 APP1 . 8 APP2 . 9 APP1 APP3 . 10 . 11 APP1 . 12 APP2 . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . 0 APP4 APP2 . 1 APP1 APP3 . 2 WCTT of VL1 . 3 APP1 . 4 APP2 . 5 APP1 APP3 . 6 . 7 APP1 . 8 APP2 . 9 APP1 APP3 . 10 . 11 APP1 . 12 APP2 . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . 0 APP4 APP2 . 1 APP1 APP3 . 2 WCTT of VL1 . Bag of VL4 (from App4): 128 3 APP1 . 4 APP2 ms . 5 APP1 APP3 . VL4 is ready when line 6 of the 6 . 7 APP1 table is executed . 8 APP2 . 9 APP1 APP3 . 10 . 11 APP1 . 12 APP2 . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . 0 APP4 APP2 . 1 APP1 APP3 . 2 WCTT of VL1 . Bag of VL4 (from App4): 128 3 APP1 . 4 APP2 ms . 5 APP1 APP3 . VL4 is ready when line 6 of the 6 . 7 APP1 table is executed . 8 APP2 VL4 will wait line 0 . 9 APP1 APP3 . 10 . 11 APP1 . 12 APP2 . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table Bag of VL4 (from App4): 128 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . ms 0 APP4 APP2 . 1 APP1 APP3 VL4 is ready when line 6 of the . 2 WCTT of VL1 table is executed . 3 APP1 . 4 APP2 VL4 will wait line 0 . 5 APP1 APP3 . 6 . 7 APP1 How to reduce this waiting delay ? . 8 APP2 . 9 APP1 APP3 . Our solution 10 . 11 APP1 To give more slots for the VLs . 12 APP2 → Oversampling of slots . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15

Our proposition One node dedicated to schedule the VLs on the ES Use of a TDMA table Bag of VL4 (from App4): 128 0 1 2 3 4 5 6 7 8 9 10 11 12 31 . ms 0 APP4 APP2 . 1 APP1 APP3 VL4 is ready when line 6 of the . 2 WCTT of VL1 table is executed . 3 APP1 . 4 APP4 APP2 VL4 will wait line 0 . 5 APP1 APP3 . 6 . 7 APP1 How to reduce this waiting delay ? . 8 APP4 APP2 . 9 APP1 APP3 . Our solution 10 . 11 APP1 To give more slots for the VLs . 12 APP4 APP2 → Oversampling of slots . 13 APP1 APP3 . 14 . 15 APP1 ……………………………………………………………………………………………………………………………… 127 APP1 APP3 J. Ermont, S. Mouysset, J.-L. Scharbarg, C. Fraboul RTNS 2018 - 10-12 october 2018 7/15