measurements of asic v2
play

Measurements of ASIC V2. M.Borri STFC Measurements in h-mode. - PowerPoint PPT Presentation

Dec 15, 2023 •239 likes •455 views

Measurements of ASIC V2. M.Borri STFC Measurements in h-mode. Overview. Test01 GOAL: Test uniformity of channel response when pulses are injected. MEASUREMENT: Loops over all the channels. Only one channel is powered up at each

  1. Measurements of ASIC V2. M.Borri STFC Measurements in h-mode.

  2. Overview. Test01 ◮ GOAL: Test uniformity of channel response when pulses are injected. ◮ MEASUREMENT: Loops over all the channels. Only one channel is powered up at each time, and pulses are injected only on this channel. Test02 ◮ GOAL: Test linearity of channel over a range of test-charges. ◮ MEASUREMENT: Loops over all the channels. Only one channel is powered up at each time. For this channel, loop over several pulse-amplitudes. For each pulse-amplitude, inject N pulses. Test03 ◮ GOAL: Test peak-time agreement with its nominal value. ◮ MEASUREMENT: Loops over all the channels. Only one channel is powered up at each time. For this channel, loop over several pulse-widths, fixed pulse-amplitude. For each pulse-width, inject N pulses. Test04 ◮ GOAL: Perform indirect measurement of the energy threshold. ◮ MEASUREMENT: Loops over all the channels. Only one channel is powered up at each time. For this channel, loop over the energy threshold. Inject N pulse for each energy threshold. ◮ Repeat for several pulse amplitudes. Testing Board 2 Chip Mode Threshold Test 1 slave hole 0x90 Test01, Test02, Test03, Test04 5 - hole 0x90 Test01, Test02, Test03, Test04 9 - hole 0x90 Test01, Test02, Test03, Test04 13 master hole 0x90 Test01, Test02, Test03, Test04

  3. Summary of results. Board 2 ∗ Nominal Chip1 Chip5 Chip9 Chip13 Test01 Pulse mean [ADC] - 2241 2232 2252 2236 Pulse std.dev. [ADC] - 1.198 1.24 1.223 1.272 Pulse counts [a.u.] 1024 1024 1024 1024 1024 Test02 Y-intercept [ADC] 204.8 226.5 217.7 236.3 210.6 Slope [ADC/eV] - 6.168e-5 6.172e-5 6.175e-5 6.192e-5 Test03 Peak time [ µ s] 7 ∼ 7 ∼ 7 ∼ 7 ∼ 7 Test04 Slope [eV/DN] 24.7 keV 2.37e+4 2.366e+04 2.371e+04 2.385e+04 * - no floating connections.

  4. Chip1 - h-mode - Test01. Pulse-mean vs channel Pulse-mean vs channel Distribution of pulse-mean Distribution of pulse-mean Entries 128 Pulse-mean [ADC] Entries [a.u.] Mean 8 2241 RMS 10.4 2260 Underflow 0 7 Overflow 0 2250 6 5 2240 4 2230 3 2220 2 1 2210 0 0 20 40 60 80 100 120 0 500 1000 1500 2000 2500 3000 3500 4000 Channel [a.u.] Pulse-mean [ADC] Pulse-Std.Dev. vs channel Pulse-Std.Dev. vs channel Distribution of pulse-std.dev. Distribution of pulse-std.dev. Entries 128 Pulse-Std.Dev. [ADC] Entries [a.u.] Mean 1.198 60 RMS 0.4897 2.5 Underflow 0 Overflow 0 50 2 40 1.5 30 20 1 10 0.5 0 0 20 40 60 80 100 120 0 500 1000 1500 2000 2500 3000 3500 4000 Channel [a.u.] Pulse-Std.Dev. [ADC] Pulse-counts vs channel Pulse-counts vs channel Distribution of pulse-counts Distribution of pulse-counts Entries 128 Pulse-counts [a.u.] Entries [a.u.] Mean 1024 1025 RMS 0 120 Underflow 0 Overflow 0 1024.8 100 1024.6 80 60 1024.4 40 1024.2 20 MODE: 1024 1024 0 0 20 40 60 80 100 120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Channel [a.u.] Pulse-counts [a.u.]

  5. Chip1 - h-mode - Test02. ADC vs injected charge ADC vs injected charge Y-intercept Y-intercept Entries 128 Mean [ADC] Entries [a.u.] Mean 226.5 9 RMS 8.597 4000 Underflow 0 8 Overflow 0 3500 7 3000 6 2500 5 4 2000 3 1500 2 1000 1 500 × 6 10 0 10 20 30 40 50 60 70 0 500 1000 1500 2000 2500 3000 3500 4000 Energy [eV] [ADC] Gradient Gradient Entries 128 Entries [a.u.] Mean 6.168e-05 RMS 1.966e-07 30 Underflow 0 Overflow 0 25 20 15 10 5 × -3 10 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Gradient [ADC/eV]

  6. Chip1 - h-mode - Test03. Peak time Peak time Mean [ADC] 2200 2000 1800 1600 1400 1200 1000 800 600 0 200 400 600 800 1000 Pulse width [10ns] Nominal peak-time is 7 µ s.

  7. Chip1 - h-mode - Test04. S-curves S-curves Threshold linearity Threshold linearity × 3 10 2200 Entries [a.u.] E-th [eV] 1000 2000 1800 800 1600 600 1400 1200 400 1000 200 800 600 0 140 160 180 200 220 240 260 150 160 170 180 190 200 E-th [DN] E-th [DN] Gradient Gradient Entries 128 Entries [a.u.] Mean 2.37e+04 2 RMS 271 Underflow 0 1.8 Overflow 0 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 Ang. coeff. [eV/DN]

  8. Chip5 - h-mode - Test01. Pulse-mean vs channel Pulse-mean vs channel Distribution of pulse-mean Distribution of pulse-mean Entries 128 Pulse-mean [ADC] Entries [a.u.] Mean 2232 2260 8 RMS 10.03 Underflow 0 7 Overflow 0 2250 6 2240 5 2230 4 2220 3 2210 2 1 2200 0 0 20 40 60 80 100 120 0 500 1000 1500 2000 2500 3000 3500 4000 Channel [a.u.] Pulse-mean [ADC] Pulse-Std.Dev. vs channel Pulse-Std.Dev. vs channel Distribution of pulse-std.dev. Distribution of pulse-std.dev. Entries 128 Pulse-Std.Dev. [ADC] Entries [a.u.] Mean 1.24 RMS 0.4947 60 Underflow 0 2.5 Overflow 0 50 2 40 30 1.5 20 1 10 0.5 0 0 20 40 60 80 100 120 0 500 1000 1500 2000 2500 3000 3500 4000 Channel [a.u.] Pulse-Std.Dev. [ADC] Pulse-counts vs channel Pulse-counts vs channel Distribution of pulse-counts Distribution of pulse-counts Entries 128 Pulse-counts [a.u.] Entries [a.u.] Mean 1024 1025 RMS 0 120 Underflow 0 Overflow 0 1024.8 100 1024.6 80 60 1024.4 40 1024.2 20 MODE: 1024 1024 0 0 20 40 60 80 100 120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Channel [a.u.] Pulse-counts [a.u.]

  9. Chip5 - h-mode - Test02. ADC vs injected charge ADC vs injected charge Y-intercept Y-intercept Entries 128 Mean [ADC] Entries [a.u.] Mean 217.7 RMS 8.548 4000 12 Underflow 0 Overflow 0 3500 10 3000 8 2500 6 2000 1500 4 1000 2 500 × 6 10 0 10 20 30 40 50 60 70 0 500 1000 1500 2000 2500 3000 3500 4000 Energy [eV] [ADC] Gradient Gradient Entries 128 Entries [a.u.] Mean 6.172e-05 25 RMS 1.988e-07 Underflow 0 Overflow 0 20 15 10 5 × -3 10 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Gradient [ADC/eV]

  10. Chip5 - h-mode - Test03. Peak time Peak time Mean [ADC] 2200 2000 1800 1600 1400 1200 1000 800 600 0 200 400 600 800 1000 Pulse width [10ns] Nominal peak-time is 7 µ s.

  11. Chip5 - h-mode - Test04. S-curves S-curves Threshold linearity Threshold linearity × 3 10 2200 Entries [a.u.] E-th [eV] 1000 2000 1800 800 1600 600 1400 1200 400 1000 200 800 600 0 140 160 180 200 220 240 260 150 160 170 180 190 200 E-th [DN] E-th [DN] Gradient Gradient Entries 128 Entries [a.u.] Mean 2.366e+04 2 RMS 254.8 Underflow 0 1.8 Overflow 1 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 Ang. coeff. [eV/DN]

  12. Chip9 - h-mode - Test01. Pulse-mean vs channel Pulse-mean vs channel Distribution of pulse-mean Distribution of pulse-mean Entries 128 Pulse-mean [ADC] Entries [a.u.] Mean 2252 10 RMS 10.48 2280 Underflow 0 Overflow 0 2270 8 2260 6 2250 2240 4 2230 2 2220 2210 0 0 20 40 60 80 100 120 0 500 1000 1500 2000 2500 3000 3500 4000 Channel [a.u.] Pulse-mean [ADC] Pulse-Std.Dev. vs channel Pulse-Std.Dev. vs channel Distribution of pulse-std.dev. Distribution of pulse-std.dev. Entries 128 Pulse-Std.Dev. [ADC] Entries [a.u.] 60 Mean 1.223 RMS 0.5285 2.5 Underflow 0 50 Overflow 0 2 40 30 1.5 20 1 10 0.5 0 0 20 40 60 80 100 120 0 500 1000 1500 2000 2500 3000 3500 4000 Channel [a.u.] Pulse-Std.Dev. [ADC] Pulse-counts vs channel Pulse-counts vs channel Distribution of pulse-counts Distribution of pulse-counts Entries 128 Pulse-counts [a.u.] Entries [a.u.] Mean 1024 1025 RMS 0 120 Underflow 0 Overflow 0 1024.8 100 1024.6 80 60 1024.4 40 1024.2 20 MODE: 1024 1024 0 0 20 40 60 80 100 120 0 200 400 600 800 1000 1200 1400 1600 1800 2000 Channel [a.u.] Pulse-counts [a.u.]

  13. Chip9 - h-mode - Test02. ADC vs injected charge ADC vs injected charge Y-intercept Y-intercept Entries 128 Mean [ADC] Entries [a.u.] Mean 236.3 9 RMS 9.033 4000 Underflow 0 8 Overflow 0 3500 7 3000 6 2500 5 4 2000 3 1500 2 1000 1 500 × 6 10 0 10 20 30 40 50 60 70 0 500 1000 1500 2000 2500 3000 3500 4000 Energy [eV] [ADC] Gradient Gradient Entries 128 Entries [a.u.] 30 Mean 6.175e-05 RMS 1.78e-07 Underflow 0 25 Overflow 0 20 15 10 5 × -3 10 0 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Gradient [ADC/eV]

  14. Chip9 - h-mode - Test03. Peak time Peak time 2400 Mean [ADC] 2200 2000 1800 1600 1400 1200 1000 800 600 0 200 400 600 800 1000 Pulse width [10ns]

  15. Chip9 - h-mode - Test04. S-curves S-curves Threshold linearity Threshold linearity × 3 10 2200 Entries [a.u.] E-th [eV] 1000 2000 1800 800 1600 600 1400 1200 400 1000 200 800 600 0 140 160 180 200 220 240 260 150 160 170 180 190 200 E-th [DN] E-th [DN] Gradient Gradient Entries 128 Entries [a.u.] Mean 2.371e+04 2 RMS 354.6 Underflow 0 1.8 Overflow 0 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 5000 10000 15000 20000 25000 30000 35000 40000 45000 50000 Ang. coeff. [eV/DN]

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

Measurements on P2 and P3 FE ASIC and Experience of P2 FE ASIC in ProtoDUNE-SP Shanshan Gao on

Measurements on P2 and P3 FE ASIC and Experience of P2 FE ASIC in ProtoDUNE-SP Shanshan Gao on

Measurements on P2 and P3 FE ASIC and Experience of P2 FE ASIC in ProtoDUNE-SP Shanshan Gao on behalf of the CE group Brookhaven National Laboratory 02/06/2020 2020/02/06 S.Gao Measurments on P2 and P3 FE ASIC 1 Outline A Brief History

665 views • 31 slides
Measurements on bare ASIC and full detector. M.Borri STFC Tests on bare asics v2.

Measurements on bare ASIC and full detector. M.Borri STFC Tests on bare asics v2.

Measurements on bare ASIC and full detector. M.Borri STFC Tests on bare asics v2. Tests on full detector. Characterization overview. Test on bare asic: Testing Sensor electrical test I-V measurement Standard tests are

325 views • 5 slides
ASIC Development @ GSI Holger Flemming Experiment Electronic / ASIC-Design 1 1 The GSI ASIC

ASIC Development @ GSI Holger Flemming Experiment Electronic / ASIC-Design 1 1 The GSI ASIC

ASIC Development @ GSI Holger Flemming Experiment Electronic / ASIC-Design 1 1 The GSI ASIC Design Group Since 2002 part of experiment electronics department 5 Team members 4 designer 1 technician CAD tools (via

449 views • 12 slides
Coercive Powers & ASIC Coercive Powers & ASIC ASIC Summer School 2011 Richard Gilbert

Coercive Powers & ASIC Coercive Powers & ASIC ASIC Summer School 2011 Richard Gilbert

Coercive Powers & ASIC Coercive Powers & ASIC ASIC Summer School 2011 Richard Gilbert Chief Executive Officer Rule of Law Institute of Australia RoLIA The Rule of Law Institute is an independent non-profit association formed to

256 views • 13 slides
ASIC Research and Development at Fermilab R. Yarema April 20, 2005 Main areas ASIC R&D

ASIC Research and Development at Fermilab R. Yarema April 20, 2005 Main areas ASIC R&D

ASIC Research and Development at Fermilab R. Yarema April 20, 2005 Main areas ASIC R&D happening in EED of PPD where we have capabilities and experience in several diverse areas. ASIC design at many silicon foundries TSMC

645 views • 39 slides
ASIC Computer-Aided Design Flow ELEC 5250/6250 ASIC Design Flow ASIC Design Flow Behavioral

ASIC Computer-Aided Design Flow ELEC 5250/6250 ASIC Design Flow ASIC Design Flow Behavioral

ASIC Computer-Aided Design Flow ELEC 5250/6250 ASIC Design Flow ASIC Design Flow Behavioral Verify Model Function VHDL/Verilog Front-End Synthesis Design DFT/BIST Gate-Level Verify & ATPG Netlist Function Full-custom IC Test

874 views • 18 slides
ASIC Physical Design Post-Layout Verification ASIC Physical Design (Standard Cell) (can also do

ASIC Physical Design Post-Layout Verification ASIC Physical Design (Standard Cell) (can also do

ASIC Physical Design Post-Layout Verification ASIC Physical Design (Standard Cell) (can also do full custom layout) Component-Level Netlist (Verilog) Std. Cell Cadence: Floorplan Layouts Encounter Chip/Block (std cells) Libraries

1.13k views • 33 slides
Market Numbers eda 2 asic 2016 Market Size Forecast Systems need to get faster Auto AND consume

Market Numbers eda 2 asic 2016 Market Size Forecast Systems need to get faster Auto AND consume

eda 2 asic Systems 2.5/3D ICs Technical AND Business Considerations Herb Reiter, eda2asic Consulting, Inc. herb@eda2asic.com, 1-408-981-5831 MEPTEC Luncheon, June 13, 2012 eda 2 asic AGENDA Introduction A few market numbers Why

746 views • 55 slides
ECE 5745 Complex Digital ASIC Design Section 1: ASIC Flow Front-End Christopher Batten School of

ECE 5745 Complex Digital ASIC Design Section 1: ASIC Flow Front-End Christopher Batten School of

ECE 5745 Complex Digital ASIC Design Section 1: ASIC Flow Front-End Christopher Batten School of Electrical and Computer Engineering Cornell University http://www.csl.cornell.edu/courses/ece5745 Multi-Level Modeling Methodologies

274 views • 11 slides
ASIC Technologies Hierarchical Design and Abstraction ASIC/SoCTechnologies and Implementation

ASIC Technologies Hierarchical Design and Abstraction ASIC/SoCTechnologies and Implementation

ASIC Technologies Hierarchical Design and Abstraction ASIC/SoCTechnologies and Implementation Design abstraction in digital circuits https://www.quora.com/What-should-be-the-best-way-to-learn-VLSI-design The taxonomy of VLSI design space We

1.1k views • 25 slides
Traditional Netlist SignOff Model ASIC Vendors ASIC Customers [Front End] [Back End] Functional

Traditional Netlist SignOff Model ASIC Vendors ASIC Customers [Front End] [Back End] Functional

Providing Physical Vision to RTL Designers Shankar Krishnamoorthy Physical Synthesis Synopsys Inc. 1 Traditional Netlist SignOff Model ASIC Vendors ASIC Customers [Front End] [Back End] Functional and Timing Closure Module Designers Block

210 views • 5 slides
Evolving ASIC Methodology to Adapt to Technology and EDA Tool Advances Tom Russell Manager ASIC

Evolving ASIC Methodology to Adapt to Technology and EDA Tool Advances Tom Russell Manager ASIC

Evolving ASIC Methodology to Adapt to Technology and EDA Tool Advances Tom Russell Manager ASIC Front-End Methodology IBM Microelectronics Agenda Technology Advances Emerging Challenges Design Tool Advances ASIC Design Methodology

452 views • 23 slides
Corporate Finance Liaison November 2013 ASIC wide issues & statistics Senate Inquiry

Corporate Finance Liaison November 2013 ASIC wide issues & statistics Senate Inquiry

Corporate Finance Liaison November 2013 ASIC wide issues & statistics Senate Inquiry ASIC Stakeholder Survey ASIC Report 371 Overview of decisions on relief applications (February to May 2013) Lodgement statistics

385 views • 20 slides
Single-Phase Electronics David Christian Strategy Top Priority is finishing ASIC

Single-Phase Electronics David Christian Strategy Top Priority is finishing ASIC

Single-Phase Electronics David Christian Strategy Top Priority is finishing ASIC development: Minor modifications planned to FE ASIC (BNL) Developing a pipelined ADC (LBNL-FNAL-BNL collaboration) Submission in June.

338 views • 30 slides
B0-6: In-depth: ETROC ASIC 402.8.4.2 Ted Liu Fermilab HL-LHC CMS CD-1 Review 23, October 2019

B0-6: In-depth: ETROC ASIC 402.8.4.2 Ted Liu Fermilab HL-LHC CMS CD-1 Review 23, October 2019

B0-6: In-depth: ETROC ASIC 402.8.4.2 Ted Liu Fermilab HL-LHC CMS CD-1 Review 23, October 2019 Brief Biographical sketch Ted Liu (Fermilab) Coordinator for front-end electronics in MTD/ETL L4 for ETL ASIC in US-MTD Relevant

412 views • 28 slides
ASICs and Front-End Motherboards ASIC schedule and ProtoDUNE Run 2 Marco Verzocchi Fermilab 6

ASICs and Front-End Motherboards ASIC schedule and ProtoDUNE Run 2 Marco Verzocchi Fermilab 6

DUNE Preliminary Design Review of ASICs and Front-End Motherboards ASIC schedule and ProtoDUNE Run 2 Marco Verzocchi Fermilab 6 February 2020 The question . Is the ASIC development schedule compatible with the desire of using final

244 views • 6 slides
FPChecker Detecting Floating-Point Exceptions in GPUs Ignacio Laguna, Harshitha Menon, Tristan

FPChecker Detecting Floating-Point Exceptions in GPUs Ignacio Laguna, Harshitha Menon, Tristan

FPChecker Detecting Floating-Point Exceptions in GPUs Ignacio Laguna, Harshitha Menon, Tristan Vanderbruggen Lawrence Livermore National Laboratory Michael Bentley, Ian Briggs, Ganesh Gopalakrishnan University of Utah Cindy Rubio Gonzlez

607 views • 31 slides
Vertex reconstruction Vertex reconstruction in large liquid scintillator detectors in large

Vertex reconstruction Vertex reconstruction in large liquid scintillator detectors in large

Vertex reconstruction Vertex reconstruction in large liquid scintillator detectors in large liquid scintillator detectors David Meyhfer March 20, 2017 Universitt Hamburg 1 / 17 Vertex reconstruction Why a vertex reconstruction? Novel

555 views • 34 slides
Composition study of ultra-high-energy cosmic rays based on the Telescope Array surface detector

Composition study of ultra-high-energy cosmic rays based on the Telescope Array surface detector

Composition study of ultra-high-energy cosmic rays based on the Telescope Array surface detector data Yana Zhezher for the Telescope Array collaboration Institute for Nuclear Research of the Russian Academy of Sciences, Moscow, Russia July 17,

674 views • 25 slides
Modeling and Analysis of Data Flow Graphs using the Digraph Real-Time Task Model Morteza

Modeling and Analysis of Data Flow Graphs using the Digraph Real-Time Task Model Morteza

Modeling and Analysis of Data Flow Graphs using the Digraph Real-Time Task Model Morteza Mohaqeqi, Jakaria Abdullah, and Wang Yi Uppsala University Ada-Europe 2016 Overview Introduction Data Flow Graphs: [ 1 , 3 ] [ 2 ] Signal processing a

508 views • 46 slides
. 1 b i b i 1 b 2 b 1 b 0 b 1 b 2 b 3 b j 1/2 1/4

. 1 b i b i 1 b 2 b 1 b 0 b 1 b 2 b 3 b j 1/2 1/4

12/9/15 Fractional Binary Numbers 2 i 2 i 1 Floating-point numbers 4 2 . 1 b i b i 1 b 2 b 1 b 0 b 1 b 2 b 3 b j 1/2 1/4 Fractional binary numbers 1/8 IEEE

602 views • 3 slides
L1B Quality Assessment Discussion T. Pagano Tuesday, February 12, 2002 1 6/24/03 AIRS L1B QA

L1B Quality Assessment Discussion T. Pagano Tuesday, February 12, 2002 1 6/24/03 AIRS L1B QA

L1B Quality Assessment Discussion T. Pagano Tuesday, February 12, 2002 1 6/24/03 AIRS L1B QA OVERVIEW Types of data in L1B QA Files Data passed from L1A intended for L2 use (e.g. geolocation) Validated using earth scene

266 views • 9 slides
First Results from the CMD-3 Detector Simon Eidelman Budker Institute of Nuclear Physics SB RAS

First Results from the CMD-3 Detector Simon Eidelman Budker Institute of Nuclear Physics SB RAS

EPS11, Grenoble July 21-27, 2011 First Results from the CMD-3 Detector Simon Eidelman Budker Institute of Nuclear Physics SB RAS and Novosibirsk State University, Novosibirsk, Russia Outline 1. Motivation 2. Experiment 3. First results 4.

489 views • 21 slides
SE SECTIO CTION N 3 GR GRAPHS & TES APHS & TESTIN TING Slides by Andrew and Anny

SE SECTIO CTION N 3 GR GRAPHS & TES APHS & TESTIN TING Slides by Andrew and Anny

SE SECTIO CTION N 3 GR GRAPHS & TES APHS & TESTIN TING Slides by Andrew and Anny with material from Vinod Rathnam, Alex Mariakakis, Krysta Yousoufian, Mike Ernst, Kellen Donohue Agenda Graphs Testing Graph = collection of

388 views • 23 slides

More recommend