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Logic synthesis for post-CMOS technologies Eleonora Testa Integrated Systems Laboratory EPFL, Lausanne, Switzerland Joint work with Mathias Soeken and Giovanni De Micheli February, 2017 Logic synthesis HDL module function ( Translate a,

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Logic synthesis for post-CMOS technologies

Eleonora Testa

Integrated Systems Laboratory — EPFL, Lausanne, Switzerland

Joint work with Mathias Soeken and Giovanni De Micheli

February, 2017

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 2

Logic synthesis

module function ( a, b, c, f); input a, b, c;

utput f;

wire w0, w1, w2; assign w0 = a & b; assign w1 = a & c; assign w2 = w0 | w1; assign f = w2; endmodule

HDL

Translate into gate level

f a b c a f b c a

Optimization & technology mapping

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 3

Logic synthesis

Optimization

I Technology independent optimization

3 more strategies 7 not specific

does not consider the technology

I Technology aware optimization

3 better results 7 not general

different for each technology

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 4

Technology aware optimization

CMOS Technologies: NAND/NOR-based

VDD A B A B OUT

Emerging Technologies:

1. different primitives
2. technological constraints

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 5

Outline

Majority-based optimization Constraint-based logic synthesis Conclusions

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 6

Outline

Majority-based optimization Constraint-based logic synthesis Conclusions

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 7

Majority-based optimization

QCA [1] MAJ INV

MAJ F A B C A F

SWD [2] MAJ INV

MAJ Z A B C IN ZN

[1] M. Houshmand et al., Genetic Algorithm based Logic Optimization for Multi-Output Majority Gate- Based Nano-electronic Circuits. In ICIS, 2009. [2] O. Zografos et al., Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS. In NANO, 2015.

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Majority-based optimization

RRAM [3] Internal resistance state Zn is a function of the previous resistance state Z, the voltage at terminal P, and the voltage at Q Zn = hPQZi

MAJ Zn P Q Z

[3] P.-E. Gaillardon et al., The programmable logic-in-memory (PLiM) computer. In DATE, 2016.

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Majority-based optimization

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 8

Majority-based optimization

Majority logic:

I hxyzi = xy _ xz _ yz = (x _ y)(x _ z)(y _ z) I hxy0i = x ^ y

hxy1i = x _ y

I Axiomatic system

Ω.C : Commutativity hxyzi = hyxzi = hzyxi Ω.M : Majority hxxzi = x hx ¯ xzi = z Ω.A : Associativity hxuhyuzii = hzuhyuxii Ω.D : Distributivity hxyhuvzii = hhxyuihxyvizi Ω.I : Inverter propagation h¯ x ¯ y ¯ zi = hxyzi

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Eleonora Testa - LSI/EPFL - Logic synthesis for post-CMOS technologies - February, 2017 8

Majority-based optimization

I Data structure for Boolean functions based on majority logic:

Majority-Inverter Graphs (MIGs)

[4] L. Amarú et al., Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic

Optimization. In DAC, 2014.

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Majority-based optimization

I Homogeneous logic network consisting of 3-input majority

nodes and regular/complemented edges

I Optimization of functions thanks to majority logic

properties [5]

MAJ MAJ MAJ

1 w x 1 y z 1 f Optimization

MAJ MAJ MAJ

1 w x 1 y z z f

[5] L. Amarú et al., Boolean logic optimization in Majority-Inverter Graphs. In DAC, 2015.

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Results: SWD

I Majority enables SWD synthesis Benchmark ADPP SWD 10nm Ref.

Impr. (x)

BKA264 6.95 × 103 3.33 × 103 0.48 HCA464 1.53 × 104 4.53 × 104 2.96 CSA464 1.45 × 104 2.84 × 105 19.51 DTM32 5.69 × 104 2.26 × 106 39.66 WTM32 4.63 × 104 2.41 × 106 52.04 DTM64 4.14 × 103 2.79 × 107 67.29 GFMUL 2.06 × 103 1.13 × 104 5.49 MAC32 5.24 × 104 3.51 × 106 67.00 DIV32 3.13 × 105 2.51 × 108 800.94 CRC32 2.52 × 103 6.42 × 103 2.55 Average 9.24 × 104 2.87 × 107 105.79

ADPP: Area-Delay-Power-Product, Impr: improvement. [2] O.Zografos et al.. Design and benchmarking of hybrid CMOS-spin wave device circuits compared to 10nm CMOS. In NANO, 2015.

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Results: RRAM

I RRAM-based circuit benefits from MIG synthesis Benchmark naïve Rewriting and compilation #N #I #R #I Impr. #R Impr. adder 1020 2844 512 1911 32.81% 259 49.41% log2 32060 78885 1597 60184 23.71% 1256 21.35% max 2865 6731 1021 4996 25.78% 579 43.29% multiplier 27062 76156 2798 56009 26.45% 419 85.03% sin 5416 12479 438 10223 18.08% 402 8.22% sqrt 24618 60691 375 49782 17.97% 323 13.87% square 18484 54704 3272 33369 39.00% 452 86.19% P 236710 608655 22760 487214 19.95% 8785 61.40%

#N: number of MIG nodes, #I: number of instructions, #R: number of RRAMs. [6] M. Soeken et al, An MIG-based compiler for programmable logic-in-memory architectures. In DAC, 2016.

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Inversion minimization

Ω.I : Inverter propagation h¯ x ¯ y ¯ zi = hxyzi

MAJ MAJ MAJ

z x y z x y x f = x y z

MAJ MAJ MAJ

z x y z x y x f = x y z Inversion minimization

1. Tree based exact algorithm
2. SAT based exact algorithm
3. Heuristic algorithm by local rewriting

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Results: QCA

I QCA-based circuits benefit from inverter minimization Benchmark #N #L #E MIG Optimized MIG Impr. #INV #QCA cells #INV #QCA cells adder 2978 12 7452 1449 87754 830 85278 2.8% log2 37582 181 78917 22481 988087 8445 931943 5.7% max 7202 27 16186 3147 194272 1107 186112 4.2% multiplier 41885 111 92904 25594 1147937 12948 1097353 4.4% sin 7890 91 17275 3823 210217 1932 202653 3.6% sqrt 52344 690 111816 28734 1383000 12840 1319424 4.6% square 19200 36 39836 17158 523156 5012 474572 9.3% Average 4.9%

#N: number of MIG nodes, #L: number of levels in the MIG not considering inverters, #E: number

f edges, #INV : number of inverters, #QCA cells: number of QCA cells, Impr: improvement of the

minimal values with respect to the initial MIG. [7] E. Testa et al., Inverter Optimization in Majority-Inverter Graphs. In NANOARCH, 2016

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Outline

Majority-based optimization Constraint-based logic synthesis Conclusions

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Constraint-based logic synthesis

Emerging Technologies:

2. technological constraints

Some examples

I Limited number of outputs for each node = limited fan-out

(e.g. optical devices)

I Limited depth (e.g. quantum computing) I Inversion distribution (e.g. RRAMs) I More than one constraint (current work)

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Constraint-based logic synthesis

Emerging Technologies:

2. technological constraints

Conventional approach

f a b c a f b c a

Optimization

When considering constraints:

f a b c a

?

Optimization & Constraints

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Constraint-based logic synthesis

Problem: Given some constraints and a Boolean function f , does there exist a circuit that can realize the function f within the given constraints? Constraint-solver

f b c a

SAT-solver 3 SAT 7 UNSAT

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Outline

Majority-based optimization Constraint-based logic synthesis Conclusions

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Conclusions

Majority-based optimization: 3 fast 3 abstract, applicable to a variety of technology 7 almost everything changes for each set of primitives 7 abstract Constraint-based logic synthesis: 3 general approach and easily extensible 3 exact solution 7 resource intensive, slow 7 requires new way of thinking