Lectures 3-4: MIPS instructions Motivation Learn how a processors - - PowerPoint PPT Presentation

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Lectures 3-4: MIPS instructions Motivation Learn how a processors - - PowerPoint PPT Presentation

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Lectures 3-4: MIPS instructions Motivation Learn how a processors native language looks like Discover the most important software-hardware interface MIPS Microprocessor without Interlocked Pipeline Stages

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Lectures 3-4: MIPS instructions

Motivation

– Learn how a processor’s ‘native’ language looks like – Discover the most important software-hardware interface

MIPS – Microprocessor without Interlocked Pipeline Stages Instruction set can be downloaded from:

– http://www.cs.wisc.edu/~larus/HP_AppA.pdf

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Outline

Instruction set Basic arithmetic & logic instructions Processor registers Getting data from the memory Control-flow instructions Method calls

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Processor instructions

Instruction set (IS): collection of all machine instructions recognized by a particular processor The instruction set abstracts away the hardware details from the programmer

– The same way as an object hides its implementation details from its users

Instruction Set Architecture (ISA): a generic processor implementation that recognizes a particular IS

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RISC – CISC machines

There are many ways of defining the hardware-software interface defined by the instruction set

– Depends on how much work the hardware is allowed to do

RISC=Reduced Instruction Set Computer CISC=Complex Instruction Set Computer High-level language (HLL): a=b+10 Assembly language:

– RISC: – CISC:

l w l w r 4, 0( r 2) # r 4=m em

  • r y[ r 2+0]

r 4, 0( r 2) # r 4=m em

  • r y[ r 2+0]

add r 5, r 4, 10 # r 5=r 4+10 add r 5, r 4, 10 # r 5=r 4+10 sw sw r 5, 0( r 3) # m em

  • r y[ r 3+0] =r 5

r 5, 0( r 3) # m em

  • r y[ r 3+0] =r 5

ADDW 3 ( R5) , ( R2) , 10 ADDW 3 ( R5) , ( R2) , 10

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Assembly language

Instructions are represented internally as binary numbers

– Very hard to make out which instruction is which

Assembly language: symbolic representation of machine instructions We use the MIPS IS, typical of a RISC processor

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Arithmetic & logical operations

Data processing instructions look like:

  • per at i on dest i nat i on var , 1st
  • per and, 2nd oper and

add a, b, c

a = b+c

sub a, b, c

a = b−c Bit-wise logical instructions: and, or , xor Shift instructions:

sl l a, b, sham t

a = b << shamt

sr l a, b, sham t

a = b >> shamt, logical shift

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Registers

IS places restrictions on instruction operands RISC processors operate on registers only Registers are internal storage locations holding program variables Size of register equals the machine’s word There is a relatively small number of registers present; MIPS has 32

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MIPS general-purpose registers

Generally, any register available for any use Conventions exist for enabling code portability Java/C variables held in registers $s0 – $s7 Temporary variables: $t 0 – $t 9 Register 0 ($zer o) is hardwired to 0 Other registers with special roles Program Counter (PC) holds address of next instruction to be executed

– Not one of the general purpose registers

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Immediate operands

MIPS has instructions with one constant (immediate) operand, e.g. addi

addi r 1, r 2, n # r 1=r 2+n r 1, r 2, n # r 1=r 2+n addi addi $s0, $zer o, n # $s0=n ( $s0 $s0, $zer o, n # $s0=n ( $s015- 0

15- 0=n; $s0

=n; $s031- 16

31- 16=0)

=0) l ui l ui $s1, n1 # $s1 $s1, n1 # $s115- 0

15- 0=0; $s1

=0; $s131- 16

31- 16=n1

=n1

  • r i
  • r i

$s1, $s1, n2 # $s1 $s1, $s1, n2 # $s115- 0

15- 0=n2; $s1

=n2; $s131- 16

31- 16=n1

=n1

Load a (small) constant into a register: Assembler pseudo-instruction l i r eg, const ant

– Translated into 1 instruction for immediates < 16bits and to more instructions for more complicated cases e.g. for a 32-bit immediate

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Getting at the data

Java: MIPS:

($s2 points to base of myObj)

Cl ass M yCl ass Cl ass M yCl ass { i nt i nt var 1, var 2; var 1, var 2; } … m yO bj m yO bj = new M yCl ass( = new M yCl ass( ) … t em p = m yO bj . var 2 t em p = m yO bj . var 2 l w l w $t 1, 4( $s2) # $t 1=m em

  • r y[ 4+$s2]

$t 1, 4( $s2) # $t 1=m em

  • r y[ 4+$s2]
  • ffset of

var2 within myObj

$s2 $s2

4 8 232 - 4 32 bits

var1 var2

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Data-transfer instructions

Load Word: Store Word: Load Byte: Store Byte:

l w l w r 1, n( r 2) # r 1=m em

  • r y[ n+r 2]

r 1, n( r 2) # r 1=m em

  • r y[ n+r 2]

sw sw r 1, n( r 2) # m em

  • r y[ n+r 2] =r 1

r 1, n( r 2) # m em

  • r y[ n+r 2] =r 1

base address

  • ffset

l b r 1, n( r 2) # r 1 l b r 1, n( r 2) # r 17- 0

7- 0= m

em

  • r y[ n+r 2]

= m em

  • r y[ n+r 2]

r 1 r 131- 8

31- 8= si gn ext ensi on

= si gn ext ensi on sb sb r 1, n( r 2) # m em

  • r y[ n+r 2] =r 1

r 1, n( r 2) # m em

  • r y[ n+r 2] =r 17- 0

7- 0

no si gn ext ensi on no si gn ext ensi on

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Memory addressing

Memory is byte addressable, but it is organised so that a word can be accessed directly Where can a word be stored?

Anywhere (unaligned), or at an mult. 4 address (aligned)?

Which is the address of a word?

byte0 byte1 byte2 byte3 1 2 3

bit 0 bit 31

Big Endian word 4 4 5 6 7 byte3 byte2 byte1 byte0 3 2 1

bit 0 bit 31

Little Endian word 4 7 6 5 4

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Instruction formats

Instruction representation composed of bit-fields Similar instructions have the same format MIPS instruction formats:

– R-format (add, sub, …)

  • p

6 5 5 16

rs rt immediate

  • p

6 5 5 5 5 6

rs rt rd shamt

Main

  • pcode

1st

  • perand

2nd

  • perand

result shift sub-function

  • pcode

func

result

– I-format (addi , l w, sw, …)

1st

  • perand
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MIPS instructions – part 2

Last time:

– Data processing instructions: add, sub, and, …

Registers only and immediate types

– Data transfer instructions: lw, sw, lb, sb – Instruction encoding

Today:

– Control transfer instructions

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Control transfers: If structures

Java: MIPS:

“branch if equal”: compare value in $s1 with value in $s2 and if equal then branch to instruction marked label

i f ( i ! =j ) i f ( i ! =j ) st m nt 1 st m nt 1 el se el se st m nt 2 st m nt 2 st m nt 3 st m nt 3 beq beq $s1, $s2, l abel 1 $s1, $s2, l abel 1 st m nt 1 st m nt 1 j l abel 2 # ski p st m nt 2 j l abel 2 # ski p st m nt 2 l abel 1: l abel 1: st m nt 2 st m nt 2 l abel 2: l abel 2: st m nt 3 st m nt 3

“if case” “else case” “follow through”

beq beq $s1, $s2, l abel $s1, $s2, l abel

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Control transfer instructions

Conditional branches, I-format:

– In assembly code label is usually a string – In machine code label is obtained from immediate value as: branch target = PC + 4 * offset Similarly:

Unconditional jump, J-format: j l abel

beq beq r 1, r 2, l abel r 1, r 2, l abel bne bne r 1, r 2, l abel # i f r 1! =r 2 go t o l abel r 1, r 2, l abel # i f r 1! =r 2 go t o l abel

4

6 5 5 16

r1 r2

  • ffset

2

6 26

target

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Loops in assembly language

Java: MIPS: Java: MIPS:

whi l e ( count ! =0) whi l e ( count ! =0) st m nt st m nt l oop: beq l oop: beq $s1, $zer o, end # $s1 hol ds count $s1, $zer o, end # $s1 hol ds count st m nt st m nt j l oop # br anch back t o l oop j l oop # br anch back t o l oop end: … end: … whi l e ( f l ag1 && f l ag2) whi l e ( f l ag1 && f l ag2) st m nt st m nt l oop: beq l oop: beq $s1, $zer o, end # $s1 hol ds f l ag1 $s1, $zer o, end # $s1 hol ds f l ag1 beq beq $s2, $zer o, end # $s2 hol ds f l ag2 $s2, $zer o, end # $s2 hol ds f l ag2 st m nt st m nt j l oop # br anch back t o l oop j l oop # br anch back t o l oop end: … end: …

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Comparisons

“Set if less than” (R-format):

– set r1 to 1 if r2<r3, otherwise set r1 to 0

Java: MIPS example:

– assume that $s1 contains i and $s2 contains j

whi l e ( i > j ) whi l e ( i > j ) st m nt st m nt

l oop: sl t l oop: sl t $t 0, $s2, $s1 # $t 0 = ( i > j ) $t 0, $s2, $s1 # $t 0 = ( i > j ) beq beq $t 0, $zer o, end # t r ue i f i <= j $t 0, $zer o, end # t r ue i f i <= j st m nt st m nt j l oop # j um p back t o l oop j l oop # j um p back t o l oop end: … end: …

sl t r 1, r 2, r 3

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Method calls

Method calls are essential even for a small program Most processors provide support for method calls Java: …

f oo( ) ; f oo( ) ; … f oo( ) ; f oo( ) ; …

call to foo at line L1 call to foo at line L2

voi d f oo( ) { voi d f oo( ) { … r et ur n; r et ur n; }

where do we return to?

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MIPS support for method calls

Jumping into the method:

– “jump and link”: set $ra to PC+4 and set PC to label – Another J-format instruction

Returning:

– “jump register”: set PC to value in register r1

j al l abel j r r 1

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Using a stack for method calls

Nested calls ⇒ must save return address to prevent

  • verwriting. Solution: use a stack in memory

to push a word: to pop a word:

cal l A cal l A … cal l B cal l B … cal l C cal l C addi addi $sp, $sp, - 4 # m

  • ve sp down

$sp, $sp, - 4 # m

  • ve sp down

sw sw $r a, 0( $sp) # save r 1 on t op of st ack $r a, 0( $sp) # save r 1 on t op of st ack sp sp ( st ack ( st ack poi nt er ) poi nt er ) C B A l w l w $r a, 0( $sp) # f et ch val ue f r om st ack $r a, 0( $sp) # f et ch val ue f r om st ack addi addi $sp, $sp, 4 # m

  • ve sp up

$sp, $sp, 4 # m

  • ve sp up

Addr

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Other uses of the stack

Stack used to save caller’s registers, so that they can be used by the callee

– “caller save” or “callee save” convention

Stack can also be used to pass and return parameters

– MIPS uses $a0 – $a4 for the first 4 word-length parameters, and $v0, $v1 for return values

return address (caller context) parameters