Lectures 3-4: MIPS instructions Motivation Learn how a processors - PowerPoint PPT Presentation

Lectures 3-4: MIPS instructions � Motivation – Learn how a processor’s ‘native’ language looks like – Discover the most important software-hardware interface � MIPS – Microprocessor without Interlocked Pipeline Stages � Instruction set can be downloaded from: – http://www.cs.wisc.edu/~larus/HP_AppA.pdf Inf2C Computer Systems - 2010-2011 1

Outline � Instruction set � Basic arithmetic & logic instructions � Processor registers � Getting data from the memory � Control-flow instructions � Method calls Inf2C Computer Systems - 2010-2011 2

Processor instructions � Instruction set (IS): collection of all machine instructions recognized by a particular processor � The instruction set abstracts away the hardware details from the programmer – The same way as an object hides its implementation details from its users � Instruction Set Architecture (ISA): a generic processor implementation that recognizes a particular IS Inf2C Computer Systems - 2010-2011 3

RISC – CISC machines � There are many ways of defining the hardware-software interface defined by the instruction set – Depends on how much work the hardware is allowed to do � RISC=Reduced Instruction Set Computer CISC=Complex Instruction Set Computer � High-level language (HLL): a=b+10 Assembly language: – RISC: l w l w r 4, 0( r 2) # r 4=m r 4, 0( r 2) # r 4=m em em or y[ r 2+0] or y[ r 2+0] add r 5, r 4, 10 # r 5=r 4+10 add r 5, r 4, 10 # r 5=r 4+10 sw sw r 5, 0( r 3) # m r 5, 0( r 3) # m em em or y[ r 3+0] =r 5 or y[ r 3+0] =r 5 – CISC: ADDW ADDW 3 ( R5) , ( R2) , 10 3 ( R5) , ( R2) , 10 Inf2C Computer Systems - 2010-2011 4

Assembly language � Instructions are represented internally as binary numbers – Very hard to make out which instruction is which � Assembly language: symbolic representation of machine instructions � We use the MIPS IS, typical of a RISC processor Inf2C Computer Systems - 2010-2011 5

Arithmetic & logical operations � Data processing instructions look like: oper and, 2 nd oper and oper at i on dest i nat i on var , 1 st a = b+c add a, b, c a = b − c sub a, b, c � Bit-wise logical instructions: and, or , xor � Shift instructions: a = b << shamt sl l a, b, sham t a = b >> shamt, logical shift sr l a, b, sham t Inf2C Computer Systems - 2010-2011 6

Registers � IS places restrictions on instruction operands � RISC processors operate on registers only � Registers are internal storage locations holding program variables � Size of register equals the machine’s word � There is a relatively small number of registers present; MIPS has 32 Inf2C Computer Systems - 2010-2011 7

MIPS general-purpose registers � Generally, any register available for any use � Conventions exist for enabling code portability � Java/C variables held in registers $s0 – $s7 � Temporary variables: $t 0 – $t 9 � Register 0 ( $zer o ) is hardwired to 0 � Other registers with special roles � Program Counter (PC) holds address of next instruction to be executed – Not one of the general purpose registers Inf2C Computer Systems - 2010-2011 8

Immediate operands � MIPS has instructions with one constant (immediate) operand, e.g. addi addi r 1, r 2, n # r 1=r 2+n r 1, r 2, n # r 1=r 2+n � Load a (small) constant into a register: addi addi $s0, $zer o, n # $s0=n ( $s0 $s0, $zer o, n # $s0=n ( $s0 15- 0 15- 0 =n; $s0 =n; $s0 31- 16 31- 16 =0) =0) � Assembler pseudo-instruction l i r eg, const ant – Translated into 1 instruction for immediates < 16bits and to more instructions for more complicated cases e.g. for a 32-bit immediate l ui l ui $s1, n1 # $s1 $s1, n1 # $s1 15- 0 15- 0 =0; $s1 =0; $s1 31- 16 31- 16 =n1 =n1 or i or i $s1, $s1, n2 # $s1 $s1, $s1, n2 # $s1 15- 0 15- 0 =n2; $s1 =n2; $s1 31- 16 31- 16 =n1 =n1 Inf2C Computer Systems - 2010-2011 9

Getting at the data � Java : Cl ass M Cl ass M yCl ass yCl ass { 32 bits i nt i nt var 1, var 2; var 1, var 2; 0 } 4 … 8 m m yO yO bj bj = new M = new M yCl ass( yCl ass( ) … $s2 $s2 t em t em p = m p = m yO yO bj . var 2 bj . var 2 var1 var2 � MIPS: ($s2 points to base of myObj) l w l w $t 1, 4( $s2) # $t 1=m $t 1, 4( $s2) # $t 1=m em em or y[ 4+$s2] or y[ 4+$s2] offset of 2 32 - 4 var2 within myObj Inf2C Computer Systems - 2010-2011 10

Data-transfer instructions offset � Load Word: base address l w l w r 1, n( r 2) # r 1=m r 1, n( r 2) # r 1=m em em or y[ n+r 2] or y[ n+r 2] � Store Word: sw sw r 1, n( r 2) # m r 1, n( r 2) # m em em or y[ n+r 2] =r 1 or y[ n+r 2] =r 1 � Load Byte: l b r 1, n( r 2) # r 1 7- 0 l b r 1, n( r 2) # r 1 7- 0 = m = m em em or y[ n+r 2] or y[ n+r 2] r 1 31- 8 r 1 31- 8 = si gn ext ensi on = si gn ext ensi on � Store Byte: sb sb r 1, n( r 2) # m r 1, n( r 2) # m em em or y[ n+r 2] =r 1 7- 0 or y[ n+r 2] =r 1 7- 0 no si gn ext ensi on no si gn ext ensi on Inf2C Computer Systems - 2010-2011 11

Memory addressing � Memory is byte addressable, but it is organised so that a word can be accessed directly � Where can a word be stored? Anywhere (unaligned), or at an mult. 4 address (aligned)? � Which is the address of a word? Big Endian Little Endian bit 31 bit 31 bit 0 bit 0 4 5 6 7 7 6 5 4 word 4 word 4 0 1 2 3 3 2 1 0 byte0 byte1 byte2 byte3 byte3 byte2 byte1 byte0 Inf2C Computer Systems - 2010-2011 12

Instruction formats � Instruction representation composed of bit-fields � Similar instructions have the same format � MIPS instruction formats: – R-format ( add , sub , …) 6 5 5 5 5 6 op rs rt rd shamt func Main 1st 2nd result shift sub-function opcode operand operand opcode – I-format ( addi , l w , sw , …) 6 5 5 16 op rs rt immediate 1st result operand Inf2C Computer Systems - 2010-2011 13

MIPS instructions – part 2 � Last time: – Data processing instructions: add, sub, and, … � Registers only and immediate types – Data transfer instructions: lw, sw, lb, sb – Instruction encoding � Today: – Control transfer instructions Inf2C Computer Systems - 2010-2011 14

Control transfers: If structures Java: “if case” i f ( i ! =j ) i f ( i ! =j ) st m st m nt 1 nt 1 “else case” el se el se st m st m nt 2 nt 2 “follow through” st m st m nt 3 nt 3 MIPS : beq $s1, $s2, l abel beq $s1, $s2, l abel “branch if equal”: compare value in $s1 with value in $s2 and if equal then branch to instruction marked label beq $s1, $s2, l abel 1 beq $s1, $s2, l abel 1 st m st m nt 1 nt 1 j l abel 2 # ski p st m j l abel 2 # ski p st m nt 2 nt 2 l abel 1: l abel 1: st m st m nt 2 nt 2 l abel 2: st m l abel 2: st m nt 3 nt 3 Inf2C Computer Systems - 2010-2011 15

Control transfer instructions � Conditional branches, I-format: beq beq r 1, r 2, l abel r 1, r 2, l abel 6 5 5 16 4 r1 r2 offset – In assembly code label is usually a string – In machine code label is obtained from immediate value as: branch target = PC + 4 * offset � Similarly: bne r 1, r 2, l abel # i f r 1! =r 2 go t o l abel bne r 1, r 2, l abel # i f r 1! =r 2 go t o l abel � Unconditional jump, J-format: j l abel 6 26 2 target Inf2C Computer Systems - 2010-2011 16

Loops in assembly language � Java: whi l e ( count ! =0) whi l e ( count ! =0) st m st m nt nt � MIPS: l oop: beq l oop: beq $s1, $zer o, end # $s1 hol ds count $s1, $zer o, end # $s1 hol ds count st m st m nt nt j l oop # br anch back t o l oop j l oop # br anch back t o l oop end: … end: … � Java: whi l e ( f l ag1 && f l ag2) whi l e ( f l ag1 && f l ag2) st m st m nt nt � MIPS: l oop: beq l oop: beq $s1, $zer o, end # $s1 hol ds f l ag1 $s1, $zer o, end # $s1 hol ds f l ag1 beq beq $s2, $zer o, end # $s2 hol ds f l ag2 $s2, $zer o, end # $s2 hol ds f l ag2 st m st m nt nt j l oop # br anch back t o l oop j l oop # br anch back t o l oop end: … end: … Inf2C Computer Systems - 2010-2011 17

Comparisons � “Set if less than” (R-format): sl t r 1, r 2, r 3 – set r1 to 1 if r2<r3, otherwise set r1 to 0 � Java: whi l e ( i > j ) whi l e ( i > j ) st m st m nt nt � MIPS example: – assume that $s1 contains i and $s2 contains j l oop: sl t l oop: sl t $t 0, $s2, $s1 # $t 0 = ( i > j ) $t 0, $s2, $s1 # $t 0 = ( i > j ) beq beq $t 0, $zer o, end # t r ue i f i <= j $t 0, $zer o, end # t r ue i f i <= j st m st m nt nt j l oop # j um j l oop # j um p back t o l oop p back t o l oop end: … end: … Inf2C Computer Systems - 2010-2011 18

Method calls � Method calls are essential even for a small program � Most processors provide support for method calls � Java: … call to foo at line L1 f oo( ) ; f oo( ) ; call to foo at line L2 … f oo( ) ; f oo( ) ; … voi d f oo( ) { voi d f oo( ) { … where do we return to? r et ur n; r et ur n; } Inf2C Computer Systems - 2010-2011 19

MIPS support for method calls � Jumping into the method: j al l abel – “jump and link”: set $ra to PC+4 and set PC to label – Another J-format instruction � Returning: j r r 1 – “jump register”: set PC to value in register r1 Inf2C Computer Systems - 2010-2011 20