Lecture 15 OUTLINE MOSFET structure & operation (qualitative) - - PowerPoint PPT Presentation

Lecture 15

OUTLINE

• MOSFET structure & operation (qualitative)
• Review of electrostatics
• The (N)MOS capacitor

El t t ti – Electrostatics – Charge vs. voltage characteristic

Reading: Chapter 6.1‐6.2.1

EE105 Fall 2007 Lecture 15, Slide 1

• Prof. Liu, UC Berkeley

The MOSFET

Metal-Oxide-Semiconductor Field-Effect Transistor: GATE LENGTH, Lg OXIDE THICKNESS, Tox Gate Source Drain Field-Effect Transistor: Substrate JUNCTION DEPTH, Xj

• M. Bohr, Intel Developer

Forum, September 2004

• Current flowing through the channel between the

source and drain is controlled by the gate voltage.

“N-channel” & “P-channel” MOSFETs

• perate in a complementary manner

“CMOS” C l t MOS

CURRENT

VTH

EE105 Fall 2007 Lecture 15, Slide 2

• Prof. Liu, UC Berkeley

“CMOS” = Complementary MOS

|GATE VOLTAGE|

N‐Channel MOSFET Structure

Circuit symbol

• The conventional gate material is heavily doped polycrystalline

silicon (referred to as “polysilicon” or “poly‐Si” or “poly”)

– Note that the gate is usually doped the same type as the source/drain Note that the gate is usually doped the same type as the source/drain, i.e. the gate and the substrate are of opposite types.

• The conventional gate insulator material is SiO2.
• To minimize current flow between the substrate (or “body”)

EE105 Fall 2007 Lecture 15, Slide 3

• Prof. Liu, UC Berkeley
• To minimize current flow between the substrate (or body )

and the source/drain regions, the p‐type substrate is grounded.

Review: Charge in a Semiconductor

• Negative charges:

– Conduction electrons (density = n) – Ionized acceptor atoms (density = NA)

• Positive charges:

– Holes (density = p) ( y p) – Ionized donor atoms (density = ND)

• The net charge density [C/cm3] in a semiconductor is
• Note that p n N

and N each can vary with position

( )

A D

N N n p q − + − = ρ

Note that p, n, ND, and NA each can vary with position.

• The mobile carrier concentrations (n and p) in the channel of

a MOSFET can be modulated by an electric field via VG.

EE105 Fall 2007 Lecture 15, Slide 4

• Prof. Liu, UC Berkeley

Channel Formation (Qualitative)

• As the gate voltage (VG) is increased, holes

are repelled away from the substrate surface

VG < VTH

are repelled away from the substrate surface.

– The surface is depleted of mobile carriers. The charge density within the depletion region is determined by the dopant ion density. y p y

• As VG increases above the threshold voltage

V a layer of conduction electrons forms at

VG ≥ VTH

VTH, a layer of conduction electrons forms at the substrate surface.

– For VG > VTH, n > NA at the surface. Th f i i “i t d” t b t The surface region is “inverted” to be n‐type.

The electron inversion layer serves as a resistive path (channel) for current to flow between the heavily doped (i e highly conductive) source and drain regions

EE105 Fall 2007 Lecture 15, Slide 5

• Prof. Liu, UC Berkeley

flow between the heavily doped (i.e. highly conductive) source and drain regions.

Voltage‐Dependent Resistor

• In the ON state, the MOSFET channel can be viewed as a resistor.
• Since the mobile charge density within the channel depends on

the gate voltage, the channel resistance is voltage‐dependent.

EE105 Fall 2007 Lecture 15, Slide 6

• Prof. Liu, UC Berkeley

Channel Length & Width Dependence

• Shorter channel length and wider channel width each yield

lower channel resistance, hence larger drain current.

– Increasing W also increases the gate capacitance, however, which limits circuit operating speed (frequency).

EE105 Fall 2007 Lecture 15, Slide 7

• Prof. Liu, UC Berkeley

Comparison: BJT vs. MOSFET

• In a BJT, current (IC) is limited by diffusion of carriers from the

emitter to the collector.

– IC increases exponentially with input voltage (VBE), because the carrier concentration gradient in the base is proportional to

T BE V

V

e

/

• In a MOSFET current (I ) is limited by drift of carriers from the
• In a MOSFET, current (ID) is limited by drift of carriers from the

source to the drain.

– ID increases ~linearly with input voltage (VG), because the carrier concentration in the channel is proportional to (VG‐VTH) In order to understand how MOSFET design parameters affect MOSFET

EE105 Fall 2007 Lecture 15, Slide 8

• Prof. Liu, UC Berkeley

In order to understand how MOSFET design parameters affect MOSFET performance, we first need to understand how a MOS capacitor works...

MOS Capacitor

• A metal‐oxide‐semiconductor structure can be considered as a

parallel‐plate capacitor, with the top plate being the positive plate, the gate insulator being the dielectric, and the p‐type semiconductor substrate being the negative plate.

• The negative charges in the semiconductor (for VG > 0) are

The negative charges in the semiconductor (for VG > 0) are comprised of conduction electrons and/or acceptor ions.

I d t d t d h th t ti l d h di t ib ti

EE105 Fall 2007 Lecture 15, Slide 9

• Prof. Liu, UC Berkeley

In order to understand how the potential and charge distributions within the Si depend on VG, we need to be familiar with electrostatics...

Gauss’ Law

ε ρ = ⋅ ∇ E

ρ is the net charge density ε is the dielectric permittivity

If the magnitude of electric field changes, there must be charge!

• In a charge‐free region, the electric field must be constant.

ε

• Gauss’ Law equivalently says that if there is a net electric field

leaving a region there must be positive charge in that region: leaving a region, there must be positive charge in that region:

∫ ∫

= ⋅ ∇

V V

dV dV E ε ρ

∫

Q dV ρ

∫ ∫

d d

∫

= ⋅ Q dS E

∫

=

V

Q dV ε ε ρ

∫ ∫

⋅ = ⋅ ∇

S V

dS E dV E

The integral of the electric field over a closed surface is proportional to the h ithi th l d l EE105 Fall 2007 Lecture 15, Slide 10

• Prof. Liu, UC Berkeley

∫

ε

charge within the enclosed volume

Gauss’ Law in 1‐D

ε ρ = = ⋅ ∇ dx dE E ε dx dx dE ε ρ = ε ' ) ' ( ) ( ) ( dx x x E x E

x x∫

+ = ε ρ

• Consider a pulse charge distribution:

x

) (x E ) (x E x ) (x ρ x

d

X X

EE105 Fall 2007 Lecture 15, Slide 11

• Prof. Liu, UC Berkeley

A

qN −

d

X

Electrostatic Potential

• The electric field (force) is related to the potential (energy):

ρ ) ( ) (

2

x x V d dV

– Note that an electron (–q charge) drifts in the direction of increasing

ε ρ ) ( ) (

2

x dx x V d dx dV E − = ⇒ − =

Note that an electron ( q charge) drifts in the direction of increasing potential:

dx dV q qE Fe − = − =

) (x V ) (x E ) (x ρ x

d

X ) ( x ) ( x X X

EE105 Fall 2007 Lecture 15, Slide 12

• Prof. Liu, UC Berkeley

A

qN −

d

X

d

X

Boundary Conditions

• Electrostatic potential must be a continuous function.

Otherwise, the electric field (force) would be infinite.

• Electric field does not have to be continuous, however.

Consider an interface between two materials: ) (

1 1

ε E

∫

= + − = ⋅

inside

Q S E S E dS E

2 2 1 1

ε ε ε x ∆ th If Q ) (

2 2

ε E then , If ⎯ ⎯ → ⎯

→ ∆x inside

Q

2 2 1 1

= + − S E S E ε ε S

1 2 2 1

ε ε = E E

EE105 Fall 2007 Lecture 15, Slide 13

• Prof. Liu, UC Berkeley

Discontinuity in electric displacement εE charge density at interface!

MOS Capacitor Electrostatics

• Gate electrode:

– Since E(x) = 0 in a metallic material, V(x) is constant. ( ) , ( )

• Gate‐electrode/gate‐insulator interface:

– The gate charge is located at this interface. E( ) h t l i id th t i l t E(x) changes to a non‐zero value inside the gate insulator.

• Gate insulator:

– Ideally, there are no charges within the gate insulator. y, g g E(x) is constant, and V(x) is linear.

• Gate‐insulator/semiconductor interface:

Si th di l t i itti it f SiO i l th th t f – Since the dielectric permittivity of SiO2 is lower than that of Si, E(x) is larger in the gate insulator than in the Si.

• Semiconductor:

EE105 Fall 2007 Lecture 15, Slide 14

• Prof. Liu, UC Berkeley

– If ρ(x) is constant (non‐zero), then V(x) is quadratic.

MOS Capacitor: VGB = 0

• If the gate and substrate materials are not the same (typically the

case), there is a built‐in potential (~1V across the gate insulator). ), p ( g )

– Positive charge is located at the gate interface, and negative charge in the Si. – The substrate surface region is depleted of holes, down to a depth Xdo

) ( ) (x ρ x

Xdo

) (x V

VS o

x

Qdep

S,o

EE105 Fall 2007 Lecture 15, Slide 15

• Prof. Liu, UC Berkeley

x

• tox

Xdo

Flatband Voltage, VFB

• The built‐in potential can be “cancelled out” by applying a gate

voltage that is equal in magnitude (but of the opposite polarity) as the built‐in potential. This gate voltage is called the flatband voltage because the resulting potential profile is flat.

) (x ρ ) (x ρ x

• t

) (x V

tox0

x

There is no net charge (i.e. ρ(x)=0) in the semiconductor under for V = V

EE105 Fall 2007 Lecture 15, Slide 16

• Prof. Liu, UC Berkeley
• tox0

the semiconductor under for VGB = VFB.

Voltage Drops across a MOS Capacitor

S

• x

FB GB

V V V V + = −

) (x V x

• t

X

• If we know the total charge within the semiconductor (Q̕S) ,

( )

tox Xd

we can find the electric field within the gate insulator (Eox) and hence the voltage drop across the gate insulator (Vox):

S

Q′ −

∫

S S

Q Q E V − ⎞ ⎜ ⎛ ′ −

where QS is the areal charge density in the semiconductor [C/cm2]

• x

S

• x

Q A E dS E ε = = ⋅

∫

• x

S

• x
• x

S

• x
• x
• x

C Q t A Q t E V = ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ = = ε

EE105 Fall 2007 Lecture 15, Slide 17

• Prof. Liu, UC Berkeley

and is the areal gate capacitance [F/cm2]

• x
• x
• x

t C ε ≡

VGB < VFB (Accumulation)

• If a gate voltage more negative than VFB is applied, then holes

will accumulate at the gate‐insulator/semiconductor interface will accumulate at the gate insulator/semiconductor interface.

) (x ρ

t

x

• tox

) (x V

• tox

Areal gate charge density [C/cm2]: x

( )

FB GB

• x

G

V V C Q − ⋅ =

Areal gate charge density [C/cm ]:

EE105 Fall 2007 Lecture 15, Slide 18

• Prof. Liu, UC Berkeley

VFB < VGB < VTH (Depletion)

• If the applied gate voltage is greater than VFB, then the

semiconductor surface will be depleted of holes. p

– If the applied gate voltage is less than VTH, the concentration of conduction electrons at the surface is smaller than NA ρ(x) ≅ ‐qNA(x)

) ( ) (x ρ x

t Xd

) (x V

• tox0

2

d d

X qN Q − =

Areal depletion charge density [C/cm2]:

x

( )

⎥ ⎤ ⎢ ⎡ − + = + = − 2 2

2 2 Si d A

• x

d A S

• x

FB GB

V V C X qN C X qN V V V V ε ε

d A dep

X qN Q =

EE105 Fall 2007 Lecture 15, Slide 19

• Prof. Liu, UC Berkeley

x

• tox

Xd

( )

⎥ ⎥ ⎦ ⎤ ⎢ ⎢ ⎣ ⎡ − + = ⇒ 1 2 1

A Si FB GB

• x
• x

Si d

N q V V C C X ε ε

VGB > VTH (Inversion)

• If the applied gate voltage is greater than VTH, then n > NA at

the semiconductor surface.

⎞ ⎛ N – At VGB = VTH, the total potential dropped in the Si is 2φB where

) (x ρ

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ =

i A T B

n N V ln φ

) (x ρ

X

) (x V x

• tox

Xd,max

) 2 ( 2 2

B A Si B FB TH

N q V V φ ε φ + + =

EE105 Fall 2007 Lecture 15, Slide 20

• Prof. Liu, UC Berkeley

x

• tox

Xd,max

2

• x

B FB TH

C V V φ + +

Maximum Depletion Depth, Xd,max

,

• As VGB is increased above VTH, VS and hence the depth of the

depletion region (Xd) increases very slowly. p g ( d) y y

– This is because n increases exponentially with VS, whereas Xd increases with the square root of VS. Thus, most of the incremental negative charge in the semiconductor comes from incremental negative charge in the semiconductor comes from additional conduction electrons rather than additional ionized acceptor atoms, when n exceeds NA.

• b

bl d h Xd can be reasonably approximated to reach a maximum value (Xd,max) for VGB ≥ VTH.

– Qdep thus reaches a maximum of Qdep max at VGB = VTH. Qdep thus reaches a maximum of Qdep,max at VGB VTH.

• If we assume that only the inversion‐layer charge increases

with increasing VGB above VTH, then

EE105 Fall 2007 Lecture 15, Slide 21

• Prof. Liu, UC Berkeley

( ) ( )

max ,

) ( so and

dep TH GB

• x

GB G TH GB

• x

inv

Q V V C V Q V V C Q + − = − − =

Q‐V Curve for MOS Capacitor

G

Q

B Si d

qN X ) 2 ( 2

max ,

φ ε =

( )

V V C Q

G

Q

A

qN

( )

TH GB

• x

inv

V V C Q − =

max , dep

Q

[ ]

V V

TH

V

FB

V

[ ]

V VGB ) 2 ( 2

max , max , B Si A d A dep

qN X qN Q φ ε − = − =

EE105 Fall 2007 Lecture 15, Slide 22

• Prof. Liu, UC Berkeley

p

Example

EE105 Fall 2007 Lecture 15, Slide 23

• Prof. Liu, UC Berkeley