Lecture 10: Sequential Networks: Implementation (Review) CSE 140: - - PowerPoint PPT Presentation

Lecture 10: Sequential Networks: Implementation

(Review) CSE 140: Components and Design Techniques for Digital Systems Spring 2014

CK Cheng, Diba Mirza

• Dept. of Computer Science and Engineering

University of California, San Diego

1

Universal*Gates*(review)*

• Is*the*following*func7on*a*universal*set*

****f(x,y)*=*xy*+x’y’* ****A.*Yes* ****B.*No* * *

2

Universal*Gates*(review)*

• Is*the*following*func7on*a*universal*set*

****f(x,y,z)*=*xyz*+x’y’z’* ****A.*Yes* ****B.*No* * *

3

Moore Design

Output is a function of present state only

Mealy Design

Output is a function of present state and input

Implementation Procedure

• 1. Draw*State*Diagram*[Mealy*or*Moore*as*required]**

* 2.*Assign*the*state,*input,*output*encoding* * 3.*Draw*State*Transi7on*Table** * 4.*Derive*Boolean*Expressions* * 5.*Draw*circuit** *

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Pattern Recognizer: A sequential machine has a binary input x in {a,b}. For x(t-2, t) = baa, the output y(t) = 1, otherwise y(t) = 0. Implement the corresponding circuit using JK flip flops Draw the Moore and Mealy state diagram

STEP 1 : Moore State Diagram

S1 S0 b b b a

S2

a a

S3 1

a b

Moore Machine

C1 C2

CLK x(t) y(t) S(t)

STEP 1 : Mealy State Diagram

S1 S0

b/0 b/0 b/0 a/1

S2

a/0 a/0

Mealy Machine

C1 C2

CLK x(t) y(t) S(t)

Looking for baa

STEP 2 : State, Input and Output Encoding

S1 S0

b/0 b/0 b/0 a/1

S2

a/0 a/0 State Encoding S0: S1: S2: Input Encoding a: 0 b: 1 PI Q: How many binary variables are needed to encode the states in the above diagram

• A. Three
• B. Two
• C. One

STEP 3: State Table

01 00

1/0 1/0 1/0 0/1

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0/0 0/0 State Encoding Q1 Q0 S0: 0 0 S1: 0 1 S2: 1 0

X(t) Q1(t) Q0(t) 0 0 1 0 0 0 1 1 0 1 1 0 1 1 0

STEP 3: State Table

State Assignment Q1 Q0 S0: 0 0 S1: 0 1 S2: 1 0

id x(t) Q1(t) Q0(t) Q1(t+1) Q0(t+1) y(t) 0 0 0 0 1 1 0 0 0 1 2 0 1 1 0 3 1 0 1 0 1 4 1 0 0 0 1 5 1 1 0 0 1 01 00

1/0 1/0 1/0 0/1

10

0/0 0/0

id x(t) Q1(t) Q0(t) Q1(t+1) Q0(t+1) y(t) …… …… …… …... 0 0 ……………...... ....................... 0 0 ………………… ………………… .………….... …………….

Mapping the variables to the Mealy circuit

C1 C2

id x(t) Q1(t) Q0(t) Q1(t+1) Q0(t+1) y(t) … … …... ....... 0 0 ………… …............. 0 0 …………………… ……………… ………….... ……………

Excitation table using JK flip flop

C1 C2 JK

x(t) y(t) Q1(t)

JK

Q0(t)

Excitation table using JK flip flop

id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) 0 0 0 0 1 1 0 0 0 1 2 0 1 1 0 3 1 0 1 0 1 4 1 0 0 0 1 5 1 1 0 0 1

0-

• 1

1 1-

1 PS NS Q(t) Q(t+1)

JK PI Q: Which of the following completely specifies the value of J0(t) in the above table?

• A. Q0(t)
• B. Q1(t), Q0(t)
• C. Q0(t), Q0(t+1)
• D. None of the above

Excitation table using JK flip flop

id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) 0 0 0 X 0 X 0 0 1 1 0 0 1 X 0 X 0 1 2 0 1 X 1 1 X 1 0 3 1 0 1 X 0 0 X 0 1 4 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1

0-

• 1

1 1-

1 PS NS Q(t) Q(t+1)

JK

STEP 4, 5: Boolean Expressions, Circuit

C1 C2 JK

x(t) y(t) Q1(t)

JK

Q0(t) id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) … … …... ....... 0 0 ………… …............. 1 0 0 1 0 0 …………………… ……………… ………….... ……………

id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) 0 0 0 X 0 X 0 0 1 1 0 0 1 X 0 X 0 1 2 0 1 X 1 1 X 1 0 3 1 0 1 X 0 0 X 0 1 4 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1

STEP 4: Boolean Expressions

0 2 6 4 1 3 7 5

K-map for J0(t):

id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) 0 0 0 X 0 X 0 0 1 1 0 0 1 X 0 X 0 1 2 0 1 X 1 1 X 1 0 3 1 0 1 X 0 0 X 0 1 4 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1

STEP 4: Boolean Expressions

0 2 6 4 1 3 7 5

K-map for J0(t):

Q1(t) Q0(t) x(t) 1 X X 1 0 X X 0

J0(t)= x(t)

id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) 0 0 0 X 0 X 0 0 1 1 0 0 1 X 0 X 0 1 2 0 1 X 1 1 X 1 0 3 1 0 1 X 0 0 X 0 1 4 1 0 0 X X 1 0 0 1 5 1 1 0 1 X X 1 0 1

STEP 4: Boolean Expressions

J0(t)= x(t) K0(t)= x(t)’ J1(t)= x(t)’Q0(t) K1(t)= 1

STEP 5: Next state Logic

C2 JK

x(t) y(t) Q1(t)

JK

Q0(t) id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) … … …... ....... 0 0 ………… …............. 0 0 …………………… ……………… ………….... …………… J0(t)= x(t) K0(t)= x(t)’ J1(t)= x(t)’Q0(t) K1(t)= 1

STEP 5: Output logic

id x(t) Q1(t) Q0(t) J0(t) K0(t) J1(t) K1(t) Q1(t+1) Q0(t+1) y(t) … … …... ....... 0 0 ………… …............. 0 0 …………………… ……………… ………….... ……………

JK

x(t) y(t) Q1(t)

JK

Q0(t) y(t)= x(t)’Q1(t) J0(t)= x(t) K0(t)= x(t)’ J1(t)= x(t)’Q0(t) K1(t)= 1

Modified 2 bit counter

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Q0(t) Q1(t)

D Q Q’ D Q Q’

CLK

x(t) Q0(t) Q1(t)

y(t)

Q: Is the above circuit a Moore or a Mealy?

• A. Moore
• B. Mealy

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Free running 2-bit counter using T-flip flops

S0* S1* S2* S3*

id Q1(t) Q0(t) T1(t) T0(t) Q1(t+1) Q0(t+1) 1 1 1 1 1 1 1 2 1 1 1 1 3 1 1 1 1

Excitation table

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T Q Q’ T Q Q’

Q0 Q1 1 T1

Free running counter with T flip flops

T0(t) = 1 T1(t) = Q0(t) Q: Notice Q1 is not fed back into the circuit. Does this mean we have only one state variable?

• A. Yes
• B. No

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Q1(t + 1) = Q0(t) + Q′

1(t)x(t),

Q0(t + 1) = Q1(t) x(t) + Q0(t)x(t), y(t) = Q′

1(t)Q0(t) + x(t)

Problem 2-II of exercise 4

Q: A state machine is described by the following equations: a) Write the state table b) Design the system with two T-flip flops and a minimal AND-OR-NOT network c) Design the system with two SR-flip flops and a minimal AND-OR-NOT network

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Q1(t + 1) = Q0(t) + Q′

1(t)x(t),

Q0(t + 1) = Q1(t) x(t) + Q0(t)x(t), y(t) = Q′

1(t)Q0(t) + x(t) id x(t) Q1(t) Q0(t) Q1(t+1) Q0(t+1) 0 0 1 0 1 2 1 0 3 1 1 4 1 0 0 5 1 0 1 6 1 1 0 7 1 1 1

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id x(t) Q1(t) Q0(t) Q1(t+1) Q0(t+1) 0 0

0**************0**

1 0 1

1**************0*

2 1 0

0**************1*

3 1 1

1**************1*

4 1 0 0

1**************1*

5 1 0 1

1**************1*

6 1 1 0 0 0 7 1 1 1 1 1

What is the next step to arrive at the circuit implementation?

• A. Draw the state diagram of the problem
• B. Obtain the excitation table
• C. Get the reduced expression for the next state as a function
• f present state and inputs

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id x(t) Q1(t) Q0(t)

S0(t) R0(t) S1(t)R1(t) Q1(t+1) Q0(t+1)

0 0

0**************0**

1 0 1

1**************0*

2 1 0

0**************1*

3 1 1

1**************1*

4 1 0 0

1**************1*

5 1 0 1

1**************1*

6 1 1 0 0 0 7 1 1 1 1 1

0- 01 1 10

1 PS NS Q(t) Q(t+1)

SR

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id x(t) Q1(t) Q0(t)

S0(t) R0(t) S1(t)R1(t) Q1(t+1) Q0(t+1)

0 0

**0**********X* **0**********X* 0**************0**

1 0 1

**0**********1* **1*********0* 1**************0*

2 1 0

**1*********0** **0*********1* 0**************1*

3 1 1

**X********0* *X*********0* 1**************1*

4 1 0 0

**1*********0* 1**********0* 1**************1*

5 1 0 1

**X*********0* 1**********0* 1**************1*

6 1 1 0 0 X 0 1 0 0 7 1 1 1 X 0 X 0 1 1

0- 01 1 10

1 PS NS Q(t) Q(t+1)

SR

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S0(t) = x(t)’Q1(t) R0(t) = x(t)’Q1(t)’ S1(t) = Q0(t)+x(t)Q1(t)’ R1(t) = Q0(t)’(x(t)+Q1(t)) y(t) = Q1(t)’ Q0(t)+x(t)

SR

x(t) y(t) Q1(t)

SR

Q0(t)

Summary: Implementation

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• Set up canonical form
• Mealy or Moore machine
• Identify the next states
• state diagram ⇨"state table
• state assignment
• Derive excitation table
• Inputs of flip flops
• Design the combinational logic
• don’t care set utilization