Layout Technique for Double-Gate Silicon Nanowire FET with an - - PowerPoint PPT Presentation

Layout Technique for Double-Gate Silicon Nanowire FET with an Efficient Sea-of-Tiles Architecture

Shashikanth Bobba

• Prof. Giovanni De Micheli

March 25, 2013

Pierre-Emmanuel, Jian Zhang, Luca, Michele, Davide, Prof. Yusuf Leblebici

Functionally Enhanced Device

Source Drain Gate

High-K Metal Gate

Gate Source Drain

Tri-gate aka FinFET Vertically stacked SiNW FET

Source Drain Gate PG CG S D

Control gate Polarity gate

Source

Drain Source

32nm 16nm 10nm

Enhanced Functionality

Double-gate Silicon Nanowire FET

! Dynamic control on the polarity of the device ! Promising feature for future reconfigurable circuits ! Ambipolar logic circuits CG PG S D CG S D CG S D p-FET n-FET

PG CG S D

Control gate Polarity gate

Source Drain

Ambipolar Logic Circuits

! Circuits based on double gate ambipolar transistors with controllable polarity (CNFET, SiNW FET, Graphene, …) ! Optimal for XOR and XNOR dominated circuits XOR2

Only 4 transistors

M-H. Ben Jamaa, PhD Thesis

CNT-DR8F

O’Connor, ICECS 07

ULM (5,3)

• K. Mohanram, DAC 12

Fewer transistors for XOR operation

Every transistor has two gates to route Motivation

XOR2 ??

Physical Design Challenges

Manufacturing Design and Architecture

Physical Synthesis Logic Synthesis DFM Verification

Arithmetic circuits Reconfigurable blocks Universal logic modules CNFET SiNW FET Graphene MoS2

E D A ! Can we use existing layout techniques? ! Logic bricks for improved Yield CG PG S D

! Introduction ! Layout Technique for DG-SiNW FET

" Motivation " Layout algorithm for XOR embedded Boolean functions

! Sea-of-Tiles ! Simulation Results ! Conclusion

Outline

Symbolic layouts : Dumbell-stick diagrams

! Need for new symbolic layouts for ambipolar circuits

!"#$%&&'()*+,, !"#$%&%'(") *#&"&$+)

!"#$%"&'()$*+' ,"##*,$*-'$"(*$.*%'

!"#$%&%'(") +"(,*&$+)

/"&)%0$1'()$*+' ,"##*,$*-'$"(*$.*%'

Control gate Polarity gate

Source Drain

Layout technique for Unate logic functions

! Negative Unate functions: NAND, NOR, AOI, OAI ! Polarity gates are biased to either Vdd or Gnd

• './0"1,232!,451%,

Vdd A A Vdd Gnd Gnd B B Out

• $./)($0)*(.#"&'/)+#'0)

1(")234)#$5)264)

A A B B Vdd Gnd Out

6,780..9%:;<) 5&#+"#7)

t1 t2 t3 t4 t1 t2 t3 t4 t1 t2 t3 t4

Layout technique for Binate logic functions

=&7*.&>05)"(,:$+) 678,451%, ?@-=)%'/.0) .#/(,') 4(A0.) #**"(#;B) !"#$%&%'(")+"(,*&$+) ?(7*.0C)"(,:$+)

A Y B B A A B B A t1 t2 t3 t4 t1 t2 t3 t4 t2 t4 t1 t3

Complex gates with embedded XOR/XNOR

#D !"#$%&%'(")+"(,*&$+)) ))))))6,780..9%:;<)5&#+"#7) F1 = (A + B)(C + D)

Gnd B Gnd A C D C D Vdd A B Vdd C D C D F1 t1 t2 t3 t4 t5 t6 t7 t8

group D : {t4, t6} group D : {t3, t5} group Vdd : {t7, t8} group Gnd : {t1, t2}

8D))))!"#$%&%'(")*#&"&$+) ;D))))!"#$%&%'(")("50"&$+) 5D))))!"#$%&%'(");B#&$&$+)

Layout Extraction

6,780..9%:;<)5&#+"#7) !"#$%&%'(")%&E&$+)F)G#/(,')+0$0"#:($) VDD GND

! Introduction ! Layout Technique for DG-SiNW FET ! Sea-of-Tiles

" Tiles as basic blocks " Optimal Tile " Power distribution for SoT

! Simulation Results ! Conclusion

Outline

Sea-of-Tiles (SoT)

Layout regularity with Tiles

232!-, 678-, !H()'"#$%&%'(")*#&"%) +"(,*05)'(+0'B0") 9.&%,

Sea-of-Tiles (SoT)

! Gate to Tile mapping

:51%(, /;, /-, /<, /=, />, /?, :;, :-, 4;, 4-, 6@A-, I$5)

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J55) I$5)

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J55) K) KL) ML) M) 6/@A-, I$5)

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J55) I$5)

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J55) K) KL) M) ML) 25/B-,

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9) I$5) K) M) I$5) J55) 2@A-, J55) 9)

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Various logic Tiles as basic building blocks

9.&%:-, 9.&%:;, 9.&%:<, 9.&%:;G-,

2314%0-'50&*6' 3

Design flow for determining the Optimal Tile

Generate Tiles Synopsys Design Compiler Library of Tiles TECHNOLOGY MAPPING Physical Synthesis onto Sea-of-Tiles Benchmark Circuits Area

Design flow for determining the Optimal Tile

Generate Tiles Synopsys Design Compiler Library of Tiles TECHNOLOGY MAPPING Physical Synthesis onto Sea-of-Tiles Benchmark Circuits Area

P P K M + A A + ? A + + P TileG2 #1 TileG2 #2

Unmapped active area

Result: Impact on Area

9.&%:-, 9.&%:;, 9.&%:<, 9.&%:;G-,

Area across various benchmarks

2@A#5&.H%B,3A%5,

• 14%
• 16%

! TileG2 and TileG1h2 optimal for mapping logic gates, with respect to reduced routing complexity thereby reducing in the overall active area

Sea-of-Tiles Power Distribution…

VDD VDD GND GND

Too much requirements in wiring

NAND XOR

Vdd A A Vdd Gnd B B Y

NAND2 XOR2

Source: S. Bobba et al, NANOARCH’12

Sea-of-Tiles Power Distribution

VDD VDD GND GND

GND GND GND GND VDD VDD VDD

Lower wiring requirements

Source: S. Bobba et al, NANOARCH’12

! Introduction ! Layout Technique for DG-SiNW FET ! Sea-of-Tiles ! Simulation Results

" Arithmetic Circuits " Circuit level Benchmarking

! Conclusion

Outline

Case study: Arithmetic Circuits

Arithmetic Cell Library Logic Gates (FO4 delay)

0 100 200 300 400 500 600 700 800 5-bit ripple-carry adder 16-bit carry-select adder (29, 3)-compressor (11, 2)-reduction tree (16 x 16 MAC) Wallace tree (54 x 54 multiplier) (31, 5) Parallel counter

Area

22.7% 22% 40% 45% 38% 22%

PG CG S D

Control gate Polarity gate

Source

Drain Source

10 20 30 5-bit ripple-carry adder 16-bit carry-select adder (29, 3)-compressor (11, 2)-reduction tree (16 x 16 MAC) Wallace tree (54 x 54 multiplier) (31, 5) Parallel counter

Case study: Arithmetic Circuits

Arithmetic Cell Library Logic Gates

Delay

66% 71.7% 66% 57.6% 61.8% 63.8%

2.8x improvement

Circuit Level Benchmarking

Generate Tiles Synopsys Design Compiler Encouter Library Characterizer TECHNOLOGY MAPPING Physical Synthesis onto Sea-of-Tiles Benchmark Circuits Delay TCAD-based table model Leakage

1.8x improvement

! Introduction ! Layout Technique for DG-SiNW FET ! Sea-of-Tiles ! Simulation Results ! Conclusion

Outline

Conclusion

! Proposed a novel layout methodology and algorithm for Boolean functions with embedded XOR ! Showed an efficient implementation of Ambipolar circuits with Sea-of-Tiles design methodology

# Area optimal tiles TileG2 and TileG1h2

! Circuit Level Benchmarking

# Maximum improvement for Arithmetic circuits (2.8x) # Reduction in Leakage power (16x)

Thank You