L e s s o n s L e a r n e d f r o m P o r t i n g H e l e n O S t o R I S C - V Martjn Děcký martjn@decky.cz February 2019
Who Am I Passionate programmer and operatjng systems enthusiast With a specifjc inclinatjon towards multjserver microkernels HelenOS developer since 2004 Research Scientjst from 2006 to 2018 Charles University (Prague), Distributed Systems Research Group Senior Research Engineer since 2017 Huawei Technologies (Munich), German Research Center, Central Sofuware Instjtute, OS Kernel Lab Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 2
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 4
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch Custom microkernel Custom user space htup://www.helenos.org Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 5
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch 3-clause BSD permissive license htups://github.com/HelenOS Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 6
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch Breath-fjrst rather than depth-fjrst Potentjally targetjng server, desktop and embedded Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 7
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch IA-32 (x86) , AMD64 (x86-64) , IA-64 (Itaninum) , ARM, MIPS, PowerPC, SPARCv9 (UltraSPARC) Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 8
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch Fine-grained modular component architecture No monolithic components even in user space Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 9
HelenOS in a Nutshell open source general-purpose multjplatgorm microkernel multjserver operatjng system designed and implemented from scratch Architecture based on a set of guiding design principles Asynchronous bi-directjonal IPC with rich semantjcs Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 10
Motjvatjon: Sofuware Dependability How HelenOS tries to achieve dependability? Microkernel multjserver architecture based on design principles Fundamental fault isolatjon (limitjng the “blast radius”) Explicit mapping between design and implementatjon Clean, manageable, understandable and auditable source code “Code is writuen once, but read many tjmes” Ratjo of comments: 38 % “Extremely well-commented source code” (Open Hub) Work in progress: Formal verifjcatjon Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 12
Motjvatjon: Sofuware Dependability High-quality implementatjon High-quality Development architecture process Verifjcatjon of correctness Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 13
monolithic OS HelenOS
HelenOS Microkernel Functjonal Blocks kernel kernel debug unit console tests kernel ELF kernel lifecycle loader log mgmt architecture independent cycle & lists, generic synchro- system tracing time trees, resource nization information support mgmt bitmaps allocator interface interrupt & hardware concurrent read- string misc syscall hash copy- resource routines routines dispatch mgmt table update address thread & slab memory work wait task space IPC allocator reservation queues queues mgmt mgmt memory thread memory frame cache capabilities zones spinlocks scheduler backends allocator coherency mgmt hardware abstraction layer shared architecture platform global page hierarchical interrupt platform I/O debugging architecture library hash table page table dependent dependent handling drivers mgmt support routines support support platform atomics shared shared bootstrap CPU context memory & platform debugging routines mgmt switching mgmt barriers drivers support Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 15
HelenOS Logical Architecture remote remote console framebufger console compositor vterm bdsh clipboard audio client session input output human interface TMPFS Location FS ISO 9660 UDF MINIX FS slip nconfsrv FAT exFAT ext4 loopip ethip tcp udp dnsrsrv dhcp fjle system device drivers link layer transport networking drivers protocols layer protocols management device vfs inetsrv manager location logger klog service naming task loader init service monitor kernel Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 16
HelenOS RISC-V Port Status January 2016 Infrastructure, boot loader, initjal virtual memory setup, kernel hand-ofg Privileged ISA Specifjcatjon version 1.7, toolchain support not upstreamed yet Targetjng Spike 18 hours net development tjme Initjal experience Many things besides the ISA itself were not nicely documented (e.g. ABI, HTIF) and had to be reverse-engineered from Spike Even some ISA details were sketchy (memory consistency model) Generally speaking, the ISA itself looked nice (except the compressed page protectjon fjeld) Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 17
HelenOS RISC-V Port Status (2) August 2017 Basic kernel functjonality (interrupt/exceptjon handling, context switching, atomics, basic I/O) Privileged ISA Specifjcatjon version 1.10 Some minor improvements (e.g. more standard page protectjon bits) Stjll targetjng Spike Observatjon: The HTIF input device has a horrible design – No interrupts – Polling requests are bufgered Stjll no decent “reference platgorm” 24 hours net development tjme Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 18
HelenOS RISC-V Port Status (3) January 2019 Towards user space support Switching to QEMU virt target Looks more reasonable than Spike CLINT, PLIC, NS16550 UART, VirtIO Toolchain support upstream 8 hours net development tjme Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 20
Lessons Learned Suprisingly litule interest in portjng HelenOS to RISC-V Compared to previous portjng efgorts to ARM, SPARCv9, SPARCv8, etc. GSoC, master thesis, team sofuware project to no avail Possible reasons Lack of feature-rich reference platgorm Lack of easily available development board A Raspberry Pi (USB, ethernet, HDMI, sound), but with a RISC-V CPU supportjng the Supervisor mode Despite RISC-V being a new major ISA, there is surprisingly litule input from operatjng system research Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 21
Problem Statement Microkernel design ideas go as back as 1969 RC 4000 Multjprogramming System nucleus (Per Brinch Hansen) Isolatjon of unprivileged processes, inter-process communicatjon, hierarchical control There are obvious benefjts of the design for safety, security, dependability, formal verifjcatjon, etc. Hardware and sofuware used to be designed independently Designing CPUs used to be an extremely complicated and costly process Operatjng systems used to be writuen afuer the CPUs were designed Hardware designs used to be rather conservatjve Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 22
Monolithic OS Design is Flawed Biggs S., Lee D., Heiser G.: The Jury Is In: Monolithic OS Design Is Flawed: Microkernel-based Designs Improve Security , ACM 9 th Asia- Pacifjc Workshop on Systems (APSys), 2018 “While intuitjve, the benefjts of the small TCB have not been quantjfjed to date. We address this by a study of critjcal Linux CVEs, where we examine whether they would be prevented or mitjgated by a microkernel-based design. We fjnd that almost all exploits are at least mitjgated to less than critjcal severity, and 40 % completely eliminated by an OS design based on a verifjed microkernel, such as seL4.” Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 23
HelenOS IPC Example naming naming service service client VFS tmpfs Martjn Děcký , FOSDEM, February 2 nd 2019 Lessons Learned from Portjng HelenOS to RISC-V 24
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