Jack Fried Cold Electronics Review October 13, 2016 10/13/2016 - - PowerPoint PPT Presentation
SBND Warm Electronics Design and Integration Test with DAQ System Jack Fried Cold Electronics Review October 13, 2016 10/13/2016 Cold Electronics Review 1 Outline SBND System Overview SBND Warm Interface Electronics Warm
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– 704 FE ASICs/704 ADC ASICs/88 Cold FPGAs – 88 Front End Mother Board assemblies – 4 sets of cold cable bundles, 4 sets of signal feed-throughs – ~22 warm interface boards
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Cold Electronics Warm Interface Electronics TPC Readout Electronics Signal Feed-through Cold Cable Back End Electronics Front End Electronics
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and control
– High speed Data
>(Nevis DAQ)
– ADC Data
– Slow control
electronics
– Program ASIC SPIs – Monitor Board voltages & currents – System debugging (real time ASIC DATA) – FEMB & WIB register control
– Timing & Synchronous Control
WIB -> FEMB
– System clock fan-out – ADC sampling clock – Synchronous commands such as calibration pulse and time stamp reset
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High speed Data Timing & Synchronous control Slow Control
– Receive data from cold electronics through cold cables – Send data to Nevis electronics over fiber optical links – Interface to slow control system using fiber GIG-E – Manage power, timing and control to cold electronics
following
– Six Warm Interface Boards (WIB)
– One Power and Timing back plane (PTB) – One Power and Timing Card (PTC)
and out other than the main power
channels
MBB (Magic Blue Box) Warm Electronics Crate (WEC)
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WIB PTB PTC WEC MBB WEC
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Arria v FPGA P-POD Cable Equalizers FEMB Quad DC/DC SFP GigE 12V Input FEMB POWER & DATA FEMB JTAG EXT Calibration
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FEMB include
– Four 1.28Gbps receiver links – I2C link (Differential LVDS) – 16MHz system clock (Differential LVDS) – SYNC/CONTROL (Differential LVDS) – FPGA JTAG signals (single ended)
DAQ electronics
through a fiber Gigabit Ethernet link using UDP
– IP address is generated by slot and crate address
independently over Ethernet
Online Monitoring
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from Magic Blue Box (MBB) system which will be distributed to the FEBs
– The WIB can generate the system clock and sync/control internally for system testing
be triggered by the Sync/Cntrl link from the (MBB) or from online monitoring
– External calibration can be accomplished by an input on the front panel of the WIB – Calibration pulse distribution is for risk mitigation only
PTB PTC MBB
System clock + Sync/Cntrl
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backplane (PTB)
– There are 5 DC/DC converters for each FEMB for a total of 20 per WIB
– Each DC/DC converter has voltage and current monitoring and can deliver up to 4A – Each DC/DC converter can be individually enabled or disabled through slow control
panel connector
PTB PTC Wiener MPOD
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From MBB To FEMB 6 WIB’s
PTC
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16 Links @ 1.28Gbps 8 Links @ 2.125Gbps FEMB FEMB FEMB FEMB
Payload (1.16Gbps) payload (1.92Gbps)
HIGH SPEED TX DATA PER LINK( FROM WIB to NEVIS DAQ)
(12bit(ADC) * 64 (Channels)) * 2MHz * 1.25 (8B/10B encoding) = 1.92Gbps Link Speed = 2.125Gbps
HIGH SPEED WIB RX DATA (FROM COLD FPGA TO WIB)
(16bit (Checksum) + (16bit (Timestamp) + 16bit (ADC ERROR) + 16bit (Reserved) + 16bit (ADC Header) + (12bit(ADC) * 32 (Channels)) * 2MHz * 1.25 (8B/10B encoding) = 1.16Gbps Link Speed = 1.28Gbps
WIB = 8(Links) * 1.92Gbps = 15.36Gbps WEC = 6(WIBs) * 15.36Gbps = 92.16Gbps
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– Can set alert triggers to be sent to online monitoring
– Can set alert triggers to be sent to online monitoring ( Such as ADC thersholds)
– WIB works as a UDP to I2C translator
– Can monitor one ASICs worth of data (16 channels)
– PRBS test pattern – Counter – Channel , Crate , Slot address encoded to aid in mapping
– Can plug a laptop containing BNL tools into the Ethernet switch or directly into a WIB – Can be used simultaneously with DAQ system – Will simplify debugging of entire system
Real-time channel data
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Power Monitor & Control
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– Each signal is a point to point connection and is individually terminated on the WIB
– Used to generate GIG-E IP address on WIB
WIB
signals from MBB
– The PTC fansout the received signals through a 1:6 clock driver delivering point to point signals to each WIB
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10/13/2016 Cold Electronics Review 16 Four 16MHz system clock fibers Four sync/control fibers One GigE link Fiber or RJ45 16MHz clock input
– MBB Electronics
evaluation board
– Simplified MBB design
– 16MHz system clock from Nevis DAQ (copper) – 2MHz ADC sampling clock goes to Nevis DAQ (copper) – Calibration signal from Nevis DAQ synced to the 2MHz clock (copper) – 5 Spare copper input signals – 5 Spare copper output signals
Crate (WEC)
– Four 16MHz system clocks one to each WEC (fiber) – Four Sync/Cntrl signals one to each WEC (fiber)
– One SFP module GIG-E which goes to
Calibration signal 2MHz ADC sampling clock
to DAQ for SBND system control
each WEC
clock from 16MHz system clock
– Sent to NEVIS DAQ
WEC
– 2MHz Clock – DC balanced pulse width modulated signal to encode synchronous commands – can encode up to seven synchronous commands
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Command Executed
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– WIB -> Nevis DAQ RACK
– Nevis timing to MBB
– MBB (DAQ RACK) -> PTC
– MBB (DAQ RACK) -> PTC
– To online monitoring – Six per WEC 24 total
– One MBB
– Nevis timing to MBB
– MBB (DAQ RACK) -> PTC
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192.168.120.001
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IP 192.168.1XX.0YY (192.168.121.1) = FEMB
– XX = Crate ID – YY = WIB Slot ID
(AABBCCDDEE00 ) = FEMB
– XX = Crate ID – YY = PTB Slot ID
KEY = 0xDEADBEEF
– 32000 write port
– 32001 read request port
– 32002 response port
– 32003 high speed data port
– 32Z00 write port
– 32Z01 read request port
– 32Z02 response port
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WIB PTB SBND PTC WEC MBB
SBND FLANGE (prototype)
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SFP SOCKET 12V POWER SBND WIB TEST ADAPTER FEMB POWER DC to DC FEMB POWER P-POD
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FEMB DATA CABLE FIBER BREAKOUT SILABS SI5338 EVAL
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XMIT transmitter module.
New Format 6U 160mm deep New Format 6U 160mm deep
New Optical Receiver Deserialiser
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Crate
DAQ PC Controller Trigger FEM Clock FEMB ASIC’s WIB Magic Blue Box (MBB) not available. Used SiLabs SI5338 eval board to emulate MBB + PTC. Fed (16 MHz) directly to WIB PCIe card Slow readout through controller (no XMIT used) Trigger sent only to controller: Asynchronous readout of WIB BNL Nevis
Optical Copper
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Calibration pulse generated in BNL's ASIC chip 1 (16 channels) read out by Nevis FEM
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Warm electronics module and its attachment to the APA frame
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monitoring
– JTAG signals rearranged to allow for an extra differential pair
– Fix clock termination “R53” wrong side of AC coupling
– Two LT2991 added
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through PTC, backplane
quad DC/DC converters to generate required voltages
receives regulated cold power directly
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Analog Motherboard FPGA Mezzanine
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Altera Cyclone V Eval Board FEMB Test Adapter Board I2C Link + High Speed Data
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SBND WIB Emulator ProtoDUNE WIB Emulator ProtoDUNE WIB Adapter