Introduction to FA challenges for Future Technologies: Nanoprobing - - PowerPoint PPT Presentation

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Introduction to FA challenges for Future Technologies: Nanoprobing Key Role

Christian Boit

TUB Berlin University of Technology, Germany EUFANET Workshop 2008 Maastricht NL Oct 2, 2008

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Extract of ITRS up to Edition 2007

SOI PD 8 (1.0) 3.5 45 2004 Beyond CMOS 3 (0.2) 7.9 11 2014 Air? 3.5 (0.3) 6.8 14 2012 Ultra Thin Body FD Dual Gates FIN FETs 4 (0.4) 5.8 18 2010 Ge / III-V Channels More of above 5 (0.6) 5.0 23 2008 Ultra low k High k Diel. Metal Gates 7 (0.8) 4.2 32 2006 Strain SiGe Raised S/D Ge S/D 9 (1.3) 3.0 65 2002 10 (1.8) 2.5 90 2000 Cu Low k SiO2 Poly Pocket / Halo Implants Bulk Si 12 (2.5) 2.2 120 1998 Interconn. Gate Active Materials Device Concepts

• Inv. Delay

(NMOS intrinsic) [ps] Perform. Clock On Chip [GHz] Min phys. Feature Size [nm] Approxim. Year of Introduction

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Laser Stimulated Electrical Signal

Optical Backside Circuit Analysis

increasing need for a high feature resolution probing tool set Detector Photon Emission Laser

• GHz regime managed by

most dynamic techniques

• Feature Size Resolution:

2 levels of analysis – Level 1: IR + SIL to identify critical area – Level 2: Nanoprobing to verify critical node – prep circuit destructive LVP

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Nanoprobing (AFP) of Identified Node

bulk-Si NW PW IMD bulk Silicon W

tungsten contacts AFP needles

• Parallel lapping down

to contact layer

• Isolated devices
• Low ohmic contact
• Destructive to circuit

Tip

L a s e r Detector Probe Tip AFM Feedback Piezo

Additonal Signals

• Resolution < 50nm

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W n-Poly p-Poly CoSi NW PW IMD p+ n+ M1 STI FIB deposited Pt

Contacts to Silicon levels – low risk of charging & of size limitation

Backside OptiFIB Circuit Edit

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FIB Backside Trench Procedure

• stopping on STI
• localized FIB trench ca. 200x200µm2

STI

up to 200x200µm2 < 400nm remaining Si ΔZ≈130nm Coaxial IR Column: planarity check of trench bottom to chip levels (fringes)

• stopping on n-wells

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bulk-Si

frontside AFP backside

NW PW IMD bulk Silicon W

tungsten contacts AFP needles

G S D FIB Pt

• parallel lapping down

to contact layer

• isolated devices
• low ohmic contact
• Destructive to circuit
• FIB backside process
• devices not isolated
• creation of new

circuit nodes

• Circuit fully functional

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UltraThin Si - Ideal Platform for NanoAnalysis

n-well STI M1 M2 ≈350nm E-Beam Techniques:

• Voltage probing

LVP, TRE

• E Beam induced photocurrent
• Dyn. LS

e-

Ultra Thin Backside Technique IR Technique Visible or UV Laser Stimulation

• Dyn. LS

Nanoprobing, C-AFM

Light Nano Probes

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Nanoscale Potential

Technique Resolution Potential Comment Optical through 500nm 150nm Limited bulk Si (IR) (SIL) resolution Nanoprobing 50nm 10nm Limited dynamics E Beam 100nm 20nm Material degradation? Optical through 300nm < 100nm Realization ultra thin Silicon (SIL) complex UV through ultra 150nm < 50nm Material thin silicon degradation?

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W FuSi

ILD

M1 Ge/III-V SiGe p+ Ge/III-V n+ STISTI SX M2 M2 etc

≅1,5µm

Cu

≅0,1µm ≅0,3µm

BOX = Buried Oxide Layer ⇒ Silicon On Insulator SOI SX

not to scale

≥ 100µm

Silicon On Insulator

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Architecture Trends

see e.g. T.Skotnicki, short course VLSI 2004 or ITRS roadmap 2003

3D ?

SOI Silicon On Insulator, PD Partially Depleted, FD Fully Depleted BOX Buried Oxide SON Silicon On Nothing GP Ground Plane DG Double Gate

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Ultra Thin Body UTB

SOI: Partially depleted = PD Fully Depleted FD

BOX Poly Gate Si

VGS = 0 |VGS| > |VT|

Deple- ted Si Conductive Channel

Subthreshold Slope ≅ 60mV / dec FD active layer ∼ 20nm => UTB

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• 20nm Gate length Technology

2 n m 50nm 40nm 20nm 2 n m 50nm 40nm 100nm 100nm

Interaction Dimensions

• Ultra thin body UTB (SOI FD / Dual Gate etc)
• Ultra Thin Silicon UTS (SOI PD)