[PPT] - Challenges for Future Cryogenic Electronics Challenges for Future PowerPoint Presentation

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Shaorui Li, Gianluigi De Geronimo, Jie Ma, Hucheng Chen, Jack Fried, Alessio D’Andragora, and Veljko Radeka Brookhaven National Laboratory, NY, USA

Challenges for Future Cryogenic Electronics Challenges for Future Cryogenic Electronics

Outline:

1. Introduction: design requirements and CMOS models.
2. CMOS Properties (300 K vs. 77K) and Lifetime in TSMC 180nm:
A. CMOS static and noise characteristics;
B. CMOS lifetime in dc operation (analog front‐end ASIC) and

in ac operation (logic circuits and FPGAs).

3. Future R&D Needs:
A. Lower technology nodes (e.g. 130 nm, 90 nm)
B. Commercial FPGA and regulators
C. Open Items

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The design of front‐end CMOS ASICs operating in cryogenic

(~ ‐200 C) environment poses some challenges. The stringent requirements include: low‐noise, low‐power, precise signal processing, and long lifetime (>20~30 years). Models:

CMOS vendors focus their models on temperature ranges from

‐40 C to 125 C and on device lifetimes of about 10 years.

The design of cryogenic front‐end ASICs for HEP requires

models capable of accurately reproducing static and dynamic response, noise performance, lifetime of CMOS devices and circuits operating in the ~ 80K range.

These models must extend to the moderate inversion region,

considering the low‐power requirements on analog circuits.

Introduction Introduction

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0.0 0.3 0.6 0.9 1.2 1.5 1.8 2 4 6 8 10 CMOS018 SIMULATED (foundry parameters) LN RT ID [mA] VDS [V] NMOS, L=0.18µm, W=10µm 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2 4 6 8 10 CMOS018 NMOS, L=0.18µm, W=10µm MEASURED LN RT ID [mA]

VDS [V]

Some differences in saturation voltage, sub-threshold slope, transconductance

ID vs VDS ID vs VGS

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CMOS018 SIMULATED (foundry parameters)

LN

RT ID gm ID [mA], gm [mS] VGS [V] NMOS, L=0.18µm, W=10µm ~18mV/dec ~72mV/dec (ln(10)nVT) 0.0 0.3 0.6 0.9 1.2 1.5 1.8 10

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~18mV/dec ~72mV/dec (ln(10)nVT) CMOS018 MEASURED ID gm LN RT ID [mA], gm [mS] VGS [V] NMOS, L=0.18µm, W=10µm

Static Characteristics: Larger Sub-Threshold Slope at 77 K Static Characteristics: Larger Sub-Threshold Slope at 77 K

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MEASURED NMOS PMOS T=300K L=360nm L=270nm L=180nm NMOS PMOS T=77K L=360nm L=270nm L=180nm

gm/ID [V

1]

Drain Current Density [mA/mm] CMOS018

Design region (approx.) for low power and low noise at 77K (moderate inversion): gm increase by a factor of ~2. Static Characteristics: Lower Power at 77K Static Characteristics: Lower Power at 77K

       K 77 T at 116 ~ K 300 T at 30 ~ T nk q I g

B D m

Favorable for cryogenic

peration:
higher gm -> lower noise
higher gm/ID -> lower power

Asymptotic value at weak inversion:

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1/f 1/f

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white NMOS ID=3.2mA (IC=1) PMOS ID=0.7mA (IC=1) fit curve L=180nm, W=1mm (20µm x 50) VDS=400mV, T=300K CMOS018

Input noise spectral density [nV/Hz] Frequency [Hz] 10

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white NMOS ID=3.2mA (IC=3) PMOS ID=0.7mA (IC=0.3) fit curve L=180nm, W=1mm (20µm x 50) VDS=400mV, T=77K CMOS018

Input noise spectral density [nV/Hz] Frequency [Hz]

comparable 1/f noise amplitude

(i.e. comparable noise at 1 Hz)

different 1/f noise slope:

PMOS > NMOS ‐> PMOS more advantageous for low‐noise application.

T = 300K T = 77K

lower white noise than at 300K
NMOS
comparable 1/f noise amplitude
Lorentzian packet
PMOS
lower 1/f noise amplitude
1/f noise slope < 1

Noise: Lower White Noise and Lower PMOS 1/f Noise at 77K Noise: Lower White Noise and Lower PMOS 1/f Noise at 77K

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300K 77K

P027sim P036 P027 P018 P027 N036 ENC [rms electrons] Gate Width [mm] CDET=200pF

PK=1s

ID=2mA P018

Input MOSFET Optimization for LAr TPC Analog Front-End ASIC Input MOSFET Optimization for LAr TPC Analog Front-End ASIC

Selected size and operating point:

riginal (simul. noise) vs. revised (meas. noise)
ID = 2 mA (3.6 mW)
W/L = 10 mm / 270 nm
IC 300K ≈ 0.4

IC 77K = 1.25

gm_300K ≈ 45 mS

gm_77K = 90 mS

Cg_300K ≈ 14 pF

Cg_77K = 18 pF 20 mm / 270 nm 0.3 1 48 mS 118mS 25 pF 28 pF

Design input PMOSFET for 200pF detector electrodes (wires)! An improvement of ENC (~530 e‐ to ~420 e‐) achieved using measured noise parameters.

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Most failure mechanisms (e.g. electromigration, stress migration, time‐

dependent dielectric breakdown, and thermal cycling) are strongly temperature dependent and become negligible at cryogenic temperature. The only remaining mechanism that may affect the lifetime of CMOS devices at cryogenic temperature is the degradation (aging) due to channel hot carrier effects (HCE).

The degradation mainly concerns NMOS devices ‐ PMOS usually exhibits a

lifetime two orders of magnitude longer than NMOS.

Lifetime due to aging: A limit defined by a chosen level of monotonic

degradation in e.g., drain current, transconductance, due to a well understood

mechanism. The device “fails” if a chosen parameter gets out of the specified

circuit design range. This aging mechanism does not result in sudden device failure.

Our study and experiments suggest that the lifetime due to HCE at cryogenic

temperature, as at room temperature, is limited by a predictable and a very gradual degradation (aging) mechanism which can be controlled by the electronic design. In this study we have been following the basics established in the literature, e.g., Hu et al. (1985), and the practices adopted more recently by Chen&Cressler et al. (2006), as well as by industry. Introduction CMOS Lifetime at Cryogenic Temperatures CMOS Lifetime at Cryogenic Temperatures

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Commercial technologies are rated > 10 years lifetime (10% gm shift) at

T = 300 K, L = Lmin, VDS = nominal VDD+5%, VGS ≈ VDS/2)

Degradation is due to impact ionization:

interface state generation & charge trap in oxide → shift in Vth and gm

HCE: Basic Mechanism HCE: Basic Mechanism

Substrate current is a monitor of impact ionization
increases with drain voltage
is higher in short channel devices
has a maximum at VGS ≈ VDS/2
A lower temperature results in increased mean free path λ increasing the

substrate current Isub and gm degradation. Degradation is independent of temperature if the product λ(VDS – VSAT) is kept constant.

Accelerated lifetime test (well‐established by foundries): transistor is placed

under a severe electric filed stress (large VDS), to reduce the lifetime due to hot‐ electron degradation to a practically observable range, by a drain source voltage considerably higher than the nominal voltage (1.8V for Lmin=180nm).

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Vds=2.8V Vds=3.0V Vds=3.2V Vds=3.2V Vds=3.1V Vds=3.0V *Ids/W [s*A/m]

Isub/Id 300K Slope ~3.10 77K Slope ~2.94

Vds=2.8V

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Measurement Type I: “Stress Plot”

 

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ds a sub ds

I W I I  

CMOS in dc Operation: Analog Front-End ASIC CMOS in dc Operation: Analog Front-End ASIC

The measured points at both 300K and 77K are very close to the characteristic

slope for the interface state generation,

0.1 0.2 0.3 0.4 0.5 0.6 1E-5 1E-3 0.1 10 1000 100000 1E7 1E9

*IDS/W (s*A/m)

1/VDS(V

1)

3.2, 3.1, 3.0, 2.8 V 1.8V Lifetime ~ 3200 yrs at Vds=1.8V, 77K 1.7V 300K 77K Vds<1.8V dsat ds m it ds

V V E q W I          1 ln    ASIC design: Vds<1.5V

The projected lifetime at 300K is ~ an order of magnitude longer than at 77K.

Reducing Vds at 77K by ~ 6% makes the lifetime equal to that at 300K. Design at low Ids/W for even longer lifetime.

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it i

a    

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Isub/W [A/m] 1/Vds [1/V] 300K 77K NMOS L=180nm, W=10µm (5x2µm), Vgs=1V

Stressed lifetime=798s at Vds=3.2V, 77K Stressed lifetime=8506s at Vds=3.2V, 300K Vds=1.8V Lifetime ~ 5500 yrs at Vds=1.8V, 77K

ASIC design: Vds<1.5V

Measurement Type II: Substrate Current Density Isub /W vs 1/Vds

3 sub

I 

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One order of magnitude in substrate current Isub corresponds to three orders
f magnitude in lifetime. At 77 K, Vds= 1.8 V projects a lifetime of ~5500 years.

L=360 nm; ‐”‐ ; Ids/W=1.0µA/µm L=9 µm L=270 nm L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm L=9 µm

Isub/W (A/

m)

1.5V 1.0V 0.5V

2 4 6 1E-20 1E-19 1E-18 1E-17 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8

1/Vds (1/V)

L=360 nm; ‐”‐ ; Ids/W=1.0µA/µm L=9 µm L=270 nm L=270 nm; Vds=1.5V; Ids/W=2.4µA/µm L=9 µm

Isub/W (A/

m)

1.5V 1.0V 0.5V

2 4 6 1E-20 1E-19 1E-18 1E-17 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8 2 4 6 1E-20 1E-19 1E-18 1E-17 1E-16 1E-15 1E-14 1E-13 1E-12 1E-11 1E-10 1E-9 1E-8

1/Vds (1/V)

Isub/W and 1/Vds distribution for all transistors in the analog front‐end ASIC for LAr

TPC (TSMC 180nm, 1.8V node) shows that all transistors are well below nominal voltage of 1.8V and at low Isub; Vds < 1.5 V results in a very long extrapolated life time.

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pre stress post stress 6000 s -> 10% gm degradation Equivalent input noise [V/sqrt(Hz)] Frequency [Hz] 10

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Equivalent input noise [V/sqrt(Hz)] Frequency [Hz] pre stress post stress 12960 s -> 2% gm degradation

Noise Degradation: Less Degradation in PMOS Noise Degradation: Less Degradation in PMOS

NMOS L=180nm, W=10µm (5x2µm)

PMOS: much less degradation than NMOS
PMOS is used in the preamp input and, by design, it is the main noise

contributor in the front‐end ASIC.

PMOS L=180nm, W=10µm (5x2µm)

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Equivalent Input noise [V/sqrt(Hz)] Frequency [Hz] pre stress post stress 920 s -> 10% gm degradation post stress 3900 s -> 15% gm degradation 10

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pre stress post stress 1500s stress -> 2% degradation of gm post stress 5000s stress -> 3.5% degradation of gm Equivalent input nosie [V/sqrt(Hz)] Frequency [Hz]

300 K 300 K 77 K 77 K

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CMOS Lifetime in AC Operation: Logic Circuits and FPGAs CMOS Lifetime in AC Operation: Logic Circuits and FPGAs

Long established (e.g. Quader&Hu et al.(1994), White&Bernstein (2006)] and

adapted by foundries: considering the ac stress as a series of short dc stresses, each for effective stress time teff during the switching cycle, strung together.

The lifetime of digital circuits (ac operation) is extended by the inverse duty

factor 1/(fck teff ) compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequencies (up to 200 MHz) which may be needed for the TPC readout.

Design guidelines for digital circuits and FPGAs: Keep the inverse duty factor

1/(fck teff ) high . Additionally, reducing Vds by 10% adds an order of magnitude margin to the lifetime.

Rough estimation of teff [Quader&Hu et al. (1994)]:
1/4 of the gate voltage rise time for NMOS
1/10 of the gate fall time for PMOS

More detailed estimation can be found in the design manuals of major foundries. An accurate estimation requires a calculation of the substrate current during the change of state.

Quader&Hu et al. (1994)

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13 TSMC 180 nm: NMOS L=180nm, W=10µm

TSMC 180 nm: 10% gm degradation

in the ‘saturated’ region;

GF 130 nm: 10% gm degradation in

the ‘early-mode’ region [Hoff et. al_FNAL, 2012].

DC operation:

Early‐mode degradation in lightly‐ doped‐drain (LDD) devices, due to accumulation of negative charge under LDD oxide spacer, which eventually saturates [Chan&Chung, 1995]. Future R&D Needs: Lower Technology Nodes (e.g. 130 nm, 90 nm) Future R&D Needs: Lower Technology Nodes (e.g. 130 nm, 90 nm)

AC operation:

A major foundry has specified a more sensitive effective stress time to drain‐ source voltage transition time, i.e. up to 5 time longer lifetime, of an inverter (fck=100 MHz) in 90 nm than in 180‐ and 130‐nm.

Vds=3.2V,77K Vds=2.8V, 77K Vds=3V,77K Vds=2.8V, RT Vds=3V,RT Vds=3.2V,RT 10

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1 10 100 gm degradation [%] Stress time [s]

How to predict lifetime from the early‐mode degradation needs further R&D.

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FPGA Lifetime: a standard method is to observe ring oscillator frequency under severe Vds

stress [Wang et al. 2006], as degradation of Ids leads to increased rise (propagation) time and reduced ring oscillator frequency. Needs further R&D.

Regulators for cryogenic operation: 1.2 V and 2.5 V for FPGA, and 1.8 V for LAr ASICs.

Selected 3 baseline devices, Globaltech GS2915L18F, TI TPS74201/74401, from a total of 19 devices (from ADI, Intersil, Linear, Maxim, National) tested. Cold longtime experiment: Globaltech GS2915L18F tested >2 years; TI TPS74201/74401 will start soon. Needs further R&D on lifetime.

Future R&D Needs: Commercial FPGA and Regulators Future R&D Needs: Commercial FPGA and Regulators

FPGA candidates for cryogenic operation:

List of FPGA screening tests: configuration (JTAG & Active Serial), embedded memory, high speed transceiver, I/O interface.

✔ ✔ ✔ ✗

Vendor Family Technology Speed

f GTX

[Gbps] # of GTX Memory [Mbit] Core Voltage [V] Status

Altera Arria GX 90 nm 3.125 4-12 1.2-4.5 1.2 Tested by BNL Altera Arria II 40 nm 6.375 8-24 2.9-16.4 0.9 Tested by BNL Altera Stratix II GX 90 nm 6.375 4-20 1.4-6.7 1.2 Tested by SMU Altera Cyclone IV E 60 nm n/a n/a 0.3-3.9 1.0, 1.2 Tested by BNL Altera Cyclone IV GX 60 nm 3.125 2-8 0.5-6.5 1.2 Tested at BNL Altera Cyclone V 60 nm 3.125 2-8 0.5-6.5 1.2 Tested by BNL Xilinx Virtex 5 65 nm 6.5 0-24 0.9-18.6 1.0 Tested by BNL

✗ ✗ ✔

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Systematic characterization and modeling of several CMOS technologies for
peration in cryogenic environments for HEP, including device response (static,

dynamic, noise, and lifetime in strong, moderate and weak inversion) and digital sub‐circuit response.

A minimum of two institutions for 3 to 5 years coordinate and develop models

for those CMOS technology nodes (130nm and below) expected to be used in future cryogenic detectors.

Investigate the cryogenic operation, modeling, and lifetime of commercial

devices, such as voltage regulators, FPGAs, memories, and data transmission circuits, in order to evaluate the need for substitute ASIC developments to cover these additional critical functions.

If commercial devices fail the cryogenic and lifetime requirements, ASICs and

integrated regulators need to be developed. Open Items on Future R&D Needs Open Items on Future R&D Needs

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Backup Slides

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Principal Findings and Design Guidelines Principal Findings and Design Guidelines

1.1. A study of hot-electron effects on the device lifetime has been performed for the TSMC NMOS 180nm technology node at 300K and 77K. Two different measurements were used: accelerated lifetime measurement under severe electric field stress by the drain- source voltage (Vds), and a separate measurement of the substrate current (Isub) as a function of 1/Vds. The former verifies the canonical very steep slope of the inverse relation between the lifetime and the substrate current , , and the latter confirms that below a certain value of Vds a lifetime margin of several orders of magnitude can be achieved for the cold electronics TPC readout. The low power ASIC design for MicroBooNE and LBNE falls naturally into this domain, where hot-electron effects are negligible. 1.2. Lifetime of digital circuits (ac operation) is extended by the inverse duty factor 1/(fck teff ), compared to dc operation. This factor is large (>100) for deep submicron technology and clock frequency needed for TPC. As an additional margin, Vds may be reduced by ~10%.

2. Extremely low failure rate (incidence) in ATLAS LAr and NA48 LKr calorimeters, over a

long time scale demonstrates on a large scale that surface mount circuit board technology withstands very well even multiple abrupt immersions in LN2 applied in board testing, and that the total failure incidence in continuous operation over time, ranging from 6 to13 years so far, is very low.

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In deep submicron NMOS (L<0.25µm) electrons can become “hot”

at any temperature, by attaining energy E>kT.

Some hot electrons exceed the energy required to create an

electron-hole pair, , resulting in impact ionization. Electrons proceed to the drain. The holes drift to the substrate. The substrate current, (1)

A very small fraction of hot electrons exceeds the energy required

to create an interface state (e.g., an acceptor-like trap), in the Si- SiO2 interface, , for electrons (~4.6eV for holes). This causes a change in the transistor characteristics (transconductance, threshold, intrinsic gain). The time required to change any important parameter (the changes in different parameters are correlated) by a specified amount (e.g., gm by -10%) is defined as the device

lifetime. It can be calculated as,

(2)

Overview of Basics on Hot-Electron Effects and NMOS Lifetime

1.3

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q = electron charge λ=electron mean free path Em= electric field Ids= drain-source current W= channel width C1, C2 - constants

It has been widely recognized that Isub is a monitor for all hot-electron effects and it is the best predictor of

device lifetime, because both observable hot electron effects (electrical and optical) are driven by a common driving force –the maximum channel electric field Em , which occurs at the drain end of the channel.

The substrate current is connected to the lifetime (defined by any arbitrary but consistent criterion) by

(3)

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2.9 3.2 1.3 ; 3.7 4.1

it i i it

a eV eV eV        ฀ ฀ ฀ ~ ~ ~

dsat ds m

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Stress Test Flow Chart and Layout of test NMOS transistors Stress Test Flow Chart and Layout of test NMOS transistors

Test transistors, NMOS L=180nm, W=10µm (5 fingers x 2µm), designed to have negligible IR drop and power dissipation <15mW in stress tests to prevent temperature change due to self- heating.

2µm

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PMOS, RT, 2% deg of gm NMOS, RT, 10% deg of gm NMOS, 77K, 10% deg of gm

Lifetime [s] 1/Vds[1/V]

Vds=1.8V

Lifetime vs 1/Vds extracted from the stress measurements Lifetime vs 1/Vds extracted from the stress measurements

PMOS shows ~2 orders of magnitude longer lifetime than NMOS.

1.7 x 107 yrs 8.9 x 104 yrs 5300 yrs

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Thermal Cycling of FE ASICs and FE Boards (for MicroBooNE) Thermal Cycling of FE ASICs and FE Boards (for MicroBooNE)

Cold motherboard with 12 ASICs populated. During extensive testing of ASICs and the motherboard, ASICs have gone through ~2000 chip*immersions in LN2, the board has been immersed ~40 times without a single failure.

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References (only a few key references, among numerous references on the subject, are given here): References (only a few key references, among numerous references on the subject, are given here):

1.

C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot-electron-induced

MOSFET degradation-model, monitor, and improvement”, IEEE Journal of Solid-State Circuits, vol. sc-20, no. 1, pp. 295-305, Feb. 1985. 2.

T. Chen, C. Zhu, L. Najafizadeh, B. Jun, A. Ahmed, R. Diestelhorst, G. Espinel, and J. D.

Cressler, “CMOS reliability issues for emerging cryogenic Lunar electronics applications,” Solid-State Electronics, vol. 50, pp. 959-963, 2006. 3. V.-H. Chan and J. E. Chung, “Two-stage hot-carrier degradation and its impact on submicron LDD NMOSFET lifetime prediction”, IEEE Tran. Electron Devices, vol. 42, no. 5,

pp. 957-962, May 1995.

4.

K. K. Ng and G. W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET’s”,

IEEE Tran. Electron Devices, vol. ed-30, no. 8, pp. 871-876, Aug. 1983. 5.

P. K. Hurley, E. Sheehan, S. Moran, and A. Mathewson, “The impact of oxide degradation
n the low frequency (1/f) noise behavior of p channel MOSFETs”, Microelectronics

Reliability, vol. 36, no. 11/12, pp. 1679-1682, 1996. 6.

K. N. Quader, E. R. Minami, W.-J. Huang, P. K. Ko, and C. Hu, “Hot-Carrier-Reliability

Design Guidelines for CMOS Logic Circuits”, IEEE Journal of Solid-State Circuits, vol. sc- 29, no. 3, pp. 253-262, March 1994. 7.

J. Wang, E. Olthof, and W. Metselaar, “Hot-Carrier Degradation Analysis Based on Ring

Oscillators”, Microelectronics Reliability, 46, pp. 1858-1863, 2006.

8.

M. White and J.B. Bernstein, “Microelectronics Reliability: Physics-of -Failure Based

Modeling and Lifetime Evaluation”, JPL Publication 08-5 2/08.

Note: Manuals for each CMOS technology node provided by major foundries (e.g. IBM) are devoted to guidelines how to maximize transistor lifetime.