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Radiation Hardened Op-amp Design for 1 Mrad TID Euntae Cho a , - PDF document

Transactions of the Korean Nuclear Society Virtual Spring Meeting July 9-10, 2020 Radiation Hardened Op-amp Design for 1 Mrad TID Euntae Cho a , Gyuseong Cho b , Inyong Kwon a a Korea Atomic Energy Research Institute b Korea Advanced Institute of


  1. Transactions of the Korean Nuclear Society Virtual Spring Meeting July 9-10, 2020 Radiation Hardened Op-amp Design for 1 Mrad TID Euntae Cho a , Gyuseong Cho b , Inyong Kwon a a Korea Atomic Energy Research Institute b Korea Advanced Institute of Science and Technology entae94@gmail.com, gscho1@kaist.ac.kr, ikwon@kaeri.re.kr 1. Introduction There is increasing demand for radiation hardening electronic circuits that can survive in radiation environments, such as nuclear facilities, space, medical equipment and severe-accident. The vulnerability of electronic circuits in radiation environments is one of the main causes in the development of nuclear electronic devices. Therefore, various studies have conducted to develop radiation hardening electronic devices [1]. This paper especially discuss an operational amplifier (op- Figure. 1. Conventional two-stage op-amp amp) among these electronic circuits. Op-amps have been widely used in electronic circuit such as pre-amplifier, integrator and so on. In addition, they are a key component of analog processing systems and an essential part of many signal systems. Recently as the demand increases for integrated circuits, analog circuit designs become more important. For these reasons, we propose a new radiation hardening two-stage op-amp with two ideas, and compare the conventional two-stage op-amp with the proposed two-stage op-amp by simulations. Figure. 2. Proposed two-stage op-amp 2. Conventional Two-stage Op-amp When the MOSFET is in radiation environments, there Figure. 1 shows a schematic of the designed two-stage are many effects on the MOSFET such as increasing the op-amp. The first stage of the two-stage op-amp consists sub-threshold leakage current, shifting the threshold of a differential pair that converts the input voltage to voltage and changing the saturation current because of current. The second stage is a common source amplifier electron-hole pairs generated in SiO 2 interface by that conducts a negative feedback with an output from incident radiation. Fortunately, total ionizing dose (TID) the drain of M 4 connected to compensating capacitor (C c ). hardly affect the PMOS, because the major carriers of C c can widen bandwidth and improve the stability. M 6 is PMOS are holes that they are not easily trapped in the responsible for reference current and forms a current silicon interface to be caused V th shift. Since NMOS is mirror with M 7 and M 8 . The current of the M 7 operate as opposite, TID has an effect on NMOS that V th is shifted the biasing of the differential amplifier and the M 8 is and leakage current is increased [2]. Therefore, we make current source of second stage. a proposed op-amp for compensating the leakage current The first stage gain ( A 1 ) of two-stage op-amp is to NMOS. A 1 = − G m1 ∙ R o1 = − g m1,2 ∙ R o1 (1) 3. Proposed Two-stage Op-amp The second stage gain ( A 2 ) of two-stage op-amp is A 2 = − G m2 ∙ R o2 = − g m5 ∙ R o2 In the proposed two-stage op-amp, we add two ideas (2) to NMOS. First, we add the compensation circuit to Final gain of the op-amp is multiplication of (1) and (2) PMOS (M 9 ). When I d of NMOS (M 7 ) decreases because of TID, the lowered I d flow the gate of M 9 . Then, I d of A = A 1 A 2 = g m1,2 ∙ R o1 ∙ g m5 ∙ R o2 M 9 increases and the increased I d flows the gate of M 7 = g m1,2 ∙ g m5 ∙ ( r 𝑝2 // r 𝑝4 ) ∙ ( r 𝑝5 // r 𝑝8 ) (3) again. It would compensate for the lowered I d of M 7 . Second, we add an additional op-amp to the gate of M 7 and connect the gate and drain of M 8. It would prevent a current drop like a diode.

  2. Transactions of the Korean Nuclear Society Virtual Spring Meeting July 9-10, 2020 Table. I. Simulation results of two-stage op-amp 1 Mrad irradiation Before irradiation Conventional Proposed Conventional Proposed op-amp op-amp op-amp op-amp 28 36 Gain (dB) 51 40 (45 %) (10 %) Phase Margin 52 60 61 62 (deg) Gain Band 76 97 41 83 Width (MHz) Figure. 3. Layout included conventional and proposed op-amps 3dB Band 0.19 1.05 1.4 1.7 Width (MHz) As shown in Figure. 3, the layout consists of and proposed op-amps using eleven pads. The total chip size is 942.8 μ m width and 956.6 μ m length. 4. Simulation Results In order to compare the op-amps in two different environments, pre-radiation and radiation by simulations. The designed op-amp fabricated in 180 nm process operates at the supply voltage of 1.8 V. V bias of the proposed op-amp is 0.8 V. I bias of conventional and proposed op-amps are 54 μ A and 84 μ A, respectively. Figure. 4. Gain versus calculated irradiation dose of 4.1 In Pre-Radiation Specification conventional and proposed op-amps the 28 dB gain with the 61° phase margin after irradiation. The conventional op-amp exhibits a gain of 51 dB with By contrast, the proposed op-amp comes out the 36 dB a 52° phase margin in pre-radiation environments. After gain with the 62° phase margin after irradiation. corner simulation, gain value drops to 46 dB when Compared to before irradiation, the gain of conventional ‘fast/fast’, and it increases to 52 dB when ‘slow/slow’. op-amp drops 45% from 51 dB to 28 dB and the gain of The proposed op-amp exhibits a gain of 40 dB with a proposed op-amp drops 10% from 40 dB to 36 dB. Figure. 60° phase margin in pre-radiation environments. After 4 shows the gain value versus the calculated irradiation corner simulation, gain value drops to 36.2 dB when dose of the conventional op-amp and the proposed op- ‘fast/fast’ , and it increases to 40.3 dB when ‘slow/slow’. amp. This shows that the proposed op-amp is highly stable in the radiation environments. 4.2 In Radiation Specification 5. Conclusion We connect an additional current source modeled by We design the radiation hardened two-stage op-amp radiation impact events to M 2 to simulate irradiation test. that compensate the leakage current using an internal op- We connect only one current source to maximize the amp when the current drop in radiation environments. experimental results, but it will be actually less impact. The simulation results show that gain drop of After looking at the papers about leakage current, we can conventional and proposed op-amps are 45% and 10% derive this equation in common [2], [3]. for 1 Mrad, respectively. It verifies that the proposed op- 𝑋 I 𝑚𝑓𝑏𝑙𝑏𝑕𝑓 𝑑𝑣𝑠𝑠𝑓𝑜𝑢 ≅ 𝐵 ( 𝑀 ) log 𝑈𝐽𝐸 + 𝐶 (4) amp compensates for leakage current better than where A is about 10 -8 and B is about 10 -9 as the initial conventional op-amp, like the theoretical predictions. After the chip is completed, we will perform 𝑿 𝟒𝟏 leakage current. The ( 𝑴 ) of M 2 is ( 𝟏.𝟐𝟗 ) . The equation irradiation tests. The irradiation tests will actually show (4) shows that the leakage current flow tens of μ A at 1 that the proposed op-amp can withstand high radiation better than the conventional op-amp in radiation Mrad. So we assume that the leakage current source environments. induced by radiation effects is 15 μ A. Next, we compare the conventional op-amp with the proposed op-amp by simulation. Table. Ⅰ shows each simulation result. The conventional op-amp comes out

  3. Transactions of the Korean Nuclear Society Virtual Spring Meeting July 9-10, 2020 Acknowledgements This work was supported in part by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT (2017M2A8A4017932 and 2020M2A8A1000830). References [1] P.W. Nicholson, Nuclear Electronics, John Wiley & Sons, Inc., London, UK, 1974, pp. 44-118. [2] S. İlik, A. Kabaoğlu, N. Şahin Solmaz and M. B. Yelten, "Modeling of Total Ionizing Dose Degradation on 180-nm n- MOSFETs Using BSIM3," in IEEE Transactions on Electron Devices , vol. 66, no. 11, pp. 4617-4622, Nov. 2019. [3] Minwoong Lee, Seongik Cho, Namho Lee, Jongyeol Kim, Radiation-tolerance analysis of I-gate n-MOSFET according to isolation oxide module in the CMOS bulk process, Microelectronic Engineering, Volume 200, 2018, Pages 45-50

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