Innovatng! Together. IP Reuse for the Masses Bob Ledzius, Founder - - PowerPoint PPT Presentation

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Innovatng! Together. IP Reuse for the Masses Bob Ledzius, Founder - - PowerPoint PPT Presentation

Oct 22, 2022 355 likes •490 views

Innovatng! Together. IP Reuse for the Masses Bob Ledzius, Founder & CEO bob@concertal.com Elements ts for or Mas ass Ac Acceptan ance SIMPLE SCALABLE ACCESSIBLE Bob Ledzius April 5, 2018 Innovatng! Together. More Com

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SLIDE 1

IP Reuse for the Masses

Bob Ledzius, Founder & CEO bob@concertal.com

Innovatng! Together.

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SLIDE 2

Elements ts for

  • r Mas

ass Ac Acceptan ance

Innovatng! Together.

Bob Ledzius April 5, 2018

SIMPLE ACCESSIBLE SCALABLE

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SLIDE 3

More Com Complex Than Ever!

1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 2008 2009 2010 2011 2012 2013 2014 2015 2016 2017 500 000 000 1 000 000 000 1 500 000 000 2 000 000 000 2 500 000 000 3 000 000 000 3 500 000 000

Transistor Count (for largest MPUs & GPUs)

Productvity Gap Afects all designs! Design Productvity

IP reuse required!

System Design Automaton Innovatng! Together.

Bob Ledzius April 5, 2018

Contnued Complexity

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SLIDE 4

New w IP Requ quests

Non

  • n-Cr
  • Critcal

al Path th IP Develop

  • pment

IP I Imports C / / C++ / / R RTL TL Verif ifcatio tio

SoC Desig ign Int Integraton Paramet eter eriz ized IP IP Desig igo

Prit itected Fuoc uoctioal ioal IP Shar ariog

  • g

Ult ltra-High IP IP Reu euse Custimiz ized Paramet eters

non-critcal path

No-Touch! ch! In Integr egrato ton Ready

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 5

New w IP Reque equests

IP I Imports C / / C++ / / R RTL TL Verif ifcatio tio

SoC Desig ign Int Integraton Paramet eter eriz ized IP IP Desig igo

Prit itected Fuoc uoctioal ioal IP Shar ariog

  • g

Ult ltra-High IP IP Reu euse Custimiz ized Paramet eters

non-critcal path

ZERO EFFORT Aut utoma maton On-Dema n-Demand! nd! Design gn & Test Bench Gener enerato ton

Au Autom

  • mated Cr

Crit itcal al Path Desig ign

  • Meth

thid ids s if Op Operatio tio

  • Ar

Arch chit itec ectu ture Tip ipilig ligy

  • Tiil

iils REQUI UIRES:

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 6

New w IP Reques equests

Integrated Sim imula laton Envir ironment

IP I Imports C / / C++ / / R RTL TL Verif ifcatio tio

SoC Desig ign Int Integraton

Inhe heri rited IP a and nd SoC D Design gn Verif ifcaton

Parameter Opt ptmiz izat aton Paramet eter eriz ized IP IP Desig igo

Prit itected Fuoc uoctioal ioal IP Shar ariog

  • g

Syothesiz izable le Full ll-Chip ip RTL Expirt Ult ltra-High IP IP Reu euse Custimiz ized Paramet eters

non-critcal path

automa mated ed cr critcal path

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 7

How Simple le?

  • Orchestrate designs by just adding IP and auto building

simulaton ready RTL design with test bench.

  • Not simply IP sttching. Designs built upon a highly

fmexible and confjgurable method o operaton and efcient architecture.

  • Designs may be simply tuned by defjning confjguraton

setngs and limitng fmexibility as desired.

  • IP wrappers translate IP to SDA method o operaton.
  • Integrated compiled simulaton engine allows or

inherited IP scripts or veri ying IP in it’s integrated orm.

  • Automatc user guide documentaton.

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 8

How Simple le?

  • Integrated compiled simulaton

engine allows or inherited IP scripts

  • r veri ying IP in it’s integrated orm.
  • Inherited oundaton and IP specifjc

tasks or aiding system simulaton and UVM build environments

  • Interactve TCL based scriptng

environment.

  • C/C++ model capable

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 9

How Accessible le?

  • Web secure accessible – no sofware installs!
  • ORCHESTRATE SoC Developer – ull hands-of

SoC/FPGA design rom PLAYERS IP library elements.

  • AUDITION IP Developer – IP specifjcaton and

import o IP and IP test benches.

  • REHEARSE Simulaton – interactve and TCL

script based simulaton environment

  • All SDA accomplished server side
  • IP source code protected untl export.
  • Controlled IP and SoC design sharing.
  • SDA ecosystem available to all project stakeholders.

Concertal Site Servers IP CM Repositories Concertal Players, Auditon, Orchestrate, and Rehearse

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 10

SDA A Val alue Prop

  • posit

iton

  • n
  • SIMPLIFY AND ACCELERATE
  • UNIQUELY COMPLIMENTARY
  • STRONGER TOGETHER
  • CONSISTENT QUALITY
  • EXPERIENCED EXPERTS

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 11

IP Reuse for

  • r th

the Mas asses! Automated ront-end SoC/FPGA design through IP reuse Secure web-based accessibility or IP providers and SoC/FPGA developers Scalable in rastructure and community

Innovatng! Together.

Bob Ledzius April 5, 2018

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SLIDE 12

THANK YOU!

Q & A

Innovatng! Together.