[PPT] - Index Generation Functions: Logic Synthesis for Pattern Matching PowerPoint Presentation

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Index Generation Functions: Logic Synthesis for Pattern Matching

Tsutomu Sasao Meiji University, Kanagawa, Japan

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.

0110000100010000101001100001000100001010 0101111101101010001101011111011010100011 1111010101110111000011110101011101110001 0001111000010001011100011110000100010111 0011110000000100010100111100000001000101 0111001001000100100101110010010001001001 0010001110001111001000100011100011110010 1111111111010001111000100011100011110010 1110111000110001011011101110001100010110 1010000110100100001110100001101001000011

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Circuit

x1

x2

x40

y1 y2 y3 y4

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Methods

1. Use a look up table.
2. Convert the table into Verilog code

and use logic synthesis tool to generate an FPGA.

3. Use Xilinx CAM IP core.
4. Use a new method.

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1. To distinguish 10 vectors, 5 bits are

sufficient, in most cases.

2. Find 5 bits to distinguish 10 vectors.
3. Given an input vector, check if there

exist a vector that matches the 5 bits.

4. If such a vector exists, check if other

bits of the vector are equal to the input.

New Method

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We have 10 vectors of 40 bits. Design a circuit for pattern matching.

0110000100010000101001100001000100001010 0101111101101010001101011111011010100011 1111010101110111000011110101011101110001 0001111000010001011100011110000100010111 0011110000000100010100111100000001000101 0111001001000100100101110010010001001001 0010001110001111001000100011100011110010 1111111111010001111000100011100011110010 1110111000110001011011101110001100010110 1010000110100100001110100001101001000011

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Index Generation Unit (IGU) Index Generation Unit (IGU)

X1 X2

Linear Circuit

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Main Memory

AUX Memory

Comparator

X2 AND

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35 35

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Incompletely Specified Index Incompletely Specified Index Generation Function Generation Function

. } 1 , { , where }, ,..., 2 , 1 { : = ⊆ → B B D k D f

n

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Number of Variables to Represent Number of Variables to Represent Incompletely Specified Index Incompletely Specified Index Generation Functions Generation Functions

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Index Generation Function

x1 x2 x3 x4 x5 x6 x7 index

1
2
3
4
5
6
7
8
9
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7 7-

Segment to BCD Converter

Segment to BCD Converter

7segments BCD

a b c d e f g

1
2
3
4
5
6
7
8
9
10

d e f a b c g

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Q: Which Segments are Necessary?

a d e f b c g

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Five Segments are Necessary { {a, a,b b,e, ,e,f f,g ,g} }

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How many variables, on the average, How many variables, on the average, are necessary to represent are necessary to represent incompletely specified index incompletely specified index generation functions with 7 variables generation functions with 7 variables and weight 10? and weight 10?

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22 functions

22 functions 978 functions

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Number of Functions

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Property Property

To represent an incompletely specified index generation function with weight k, variables are sufficient, for most cases, when Example: When k=127.

3

) 1 ( log 2

2

− + k

. 7 ≥ k

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3 7 2 3 ) 1 ( log 2

2

= − × = − + k

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If each column has at most one non If each column has at most one non-

zero

zero element in a decomposition chart, then element in a decomposition chart, then f f can be represented with only the column can be represented with only the column variables variables.

.

1

x

4

x

2

x

3

x

2 3 4 1

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1

x

2 1 2 1 2 1 2 1

2 3 4 1 x x x x x x x x f ⋅ ∨ ⋅ ∨ ⋅ ∨ ⋅ =

2

x

4

x

3

x

2 3 4 1 1 1 1 4 4 4 3 3 3 2 2 2

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1

x

4

x

2

x

3

x

4 2 3 1

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If the element 4 is moved right two squares,

then f is represented by only x1 and x2 1

x

4

x

2

x

3

x

4

2

4 3

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A linear transformation permutes elements.

4 4 3 3 4 2 2 4 1 1

x y x y x x y x x y = = ⊕ = ⊕ =

1

y

4

x

2

y

3

x

2 3 4 1 4

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In this case, each column has at most one non-zero element.

4 4 3 3 4 2 2 4 1 1

x y x y x x y x x y = = ⊕ = ⊕ =

1

y

4

x

2

y

3

x

2 3 4 1

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General Function Linear Function p

n X q

Linear Decomposition Linear Decomposition

Cost: np Cost: q2p

23

)

1 (

2

+ = k log q

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‣ General form: ‣ Compound degree: The number of coefficients with ai=1 . ‣ A variable with the compound degree 1 is primitive.

Compound Variables Compound Variables

n nx

a x a x a y ⊕ ⊕ ⊕ =

2

2 1 1

} 1 , { ∈

i

a

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Linear Circuits Linear Circuits

1 1 1 j i

x x y ⊕ =

n n

MUX MUX

n n

MUX MUX

+ +

jp ip p

x x y ⊕ =

1 1 i

x y =

n

MUX ip p

x y =

n

MUX

Compound degree 2 Compound degree 1

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1 1-

out
ut-
of
f-
7 code to Index Converter

7 code to Index Converter

1-out-of-7 code

x7 x6x5 x4x3x2x1

Index

0 0 0 0 0 0 1

1 0 0 0 0 0 1 0

2 0 0 0 0 1 0 0

3 0 0 0 1 0 0 0

4 0 0 1 0 0 0 0

5 0 1 0 0 0 0 0

6 1 0 0 0 0 0 0

7

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Distribution is Skewed Distribution is Skewed

‣ For each xi, there is single 1, and 6 0‚s.

1-out-of-7 code x7 x6x5 x4x3x2x1

Index

0 0 0 0 0 0 1

1 0 0 0 0 0 1 0

2 0 0 0 0 1 0 0

3 0 0 0 1 0 0 0

4 0 0 1 0 0 0 0

5 0 1 0 0 0 0 0

6 1 0 0 0 0 0 0

7

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Only Three Variables are Only Three Variables are Necessary. Necessary.

7 6 5 4 3 7 6 3 2 2 7 5 3 1 1

x x x x y x x x x y x x x x y ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕ =

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Original Original vs.

vs. Transformed

Transformed Variables Variables

Transformed variables For each of y1,y2,y3, there are 3 0‚s, and 4 1‚s.

x7 x6x5 x4x3x2x1 y3 y2 y1

0 0 0 0 0 0 1

0 0 1

0 0 0 0 0 1 0

0 1 0

0 0 0 0 1 0 0

0 1 1

0 0 0 1 0 0 0

1 0 0

0 0 1 0 0 0 0

1 0 1

0 1 0 0 0 0 0

1 1 0

1 0 0 0 0 0 0

1 1 1

7 6 5 4 3 7 6 3 2 2 7 5 3 1 1

x x x x y x x x x y x x x x y ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕ = ⊕ ⊕ ⊕ =

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Linear Decomposition Linear Decomposition

Linear

Function

General Function

7 3 3

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# of Variables to Represent IP Address # of Variables to Represent IP Address Tables ( Tables (n n=32) =32)

k

t=1 t=2 t=3

1670

18 17 16

3288

20 19 18

4591

21 20 19

7903

23 21 20

31

t : Compound degree

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Scanning Engine for Computer Scanning Engine for Computer Virus Virus

‣ Stores k=1.3 million virus sub-patterns

f n=40 bits.

‣ The single LUT realization requires 21 Tera bits. ‣ Our method requires only 160 Mega bits.

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Memory

Reg.

Input (text) Output 8 8

k

2

log

Reg.

8

Reg.

8

Reg.

8 8 8 8

Reg.

8 8

Circuit to Detect Suspicious Patterns

5 characters 40 bits, 1.3 million patterns

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H. Nakahara, T. Sasao, M. Matsuura, "A low-cost and high-performance

virus scanning engine using a binary CAM emulator and an MPU," 8th International Symposium on Applied Reconfigurable Computing, (ARC 2012), March 19-23, 2012, Hong-Kong.

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Current Projects

‣ Minimizers for input variables

— high-speed applications — exact minimum

‣ Functional decomposition

— using multiple IGUs

‣ New applications

— Replacement for CAMs — Large-scale search engine

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Reference Reference

‣ T. Sasao, Memory-Based Logic Synthesis, Springer 2011.

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