Lecture 25 Built-In Self-Testing Pattern Generation and Response - - PowerPoint PPT Presentation

Lecture 25 Built-In Self-Testing Pattern Generation and Response Pattern Generation and Response Compaction

Motivation and economics Definitions Definitions Built-in self-testing (BIST) process BIST pattern generation (PG) BIST pattern generation (PG) BIST response compaction (RC) BILBO BILBO

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BIST Motivation

Specify test as one of the system functions self-test Useful for field test and diagnosis (less expensive than Useful for field test and diagnosis (less expensive than

a local automatic test equipment)

Software tests for field test and diagnosis:

g

Low hardware fault coverage Low diagnostic resolution

g

Slow to operate

Hardware BIST benefits:

Lower system test effort Improved system maintenance and repair Improved component repair Better diagnosis

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Costly Test Problems Alleviated S by BIST

Increasing chip logic-to-pin ratio: harder observability Increasing chip logic-to-pin ratio: harder observability Increasingly dense devices and faster clocks Increasing test generation and application times Increasing test generation and application times Increasing size of test vectors stored in ATE Expensive ATE needed for 1 GHz clocking chips

p g p

Hard testability insertion– designers unfamiliar with

gate-level logic, since they design at behavioral level

In-circuit testing no longer technically feasible Shortage of test engineers

Ci i i b il i i d

Circuit testing cannot be easily partitioned

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Typical Quality Requirements yp Q y q

98% single stuck-at fault coverage 100% interconnect fault coverage Reject ratio – 1 in 100,000

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Benefits and Costs of BIST with DFT

Des Design and and test test Fa Fabri- ca cation tion Man Manuf. Te Test Le Level Maint intenance enance te test Diagnosis nosis and and r repa pair ir Ser Servic ice inter interruption uption + / - + / - +

• +
• Chip

Chips + / - + / - +

• +
• Boa

Boards

• + /

+ / - +

• +
• Syste

System

• C

C t i i + C Cos

• st i

t incr ncrease ease

• Cost sa
• st saving

ving +/- +/- Cost incr

• st increase

ease may balance may balance cost r cost reduction eduction

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Economics – BIST Costs

Chip area overhead for:

Test controller Test controller Hardware pattern generator Hardware response compacter Hardware response compacter Testing of BIST hardware

Pin overhead: At least 1 pin needed to activate BIST operation

Pin overhead: At least 1 pin needed to activate BIST operation

Performance overhead: extra path delays due to BIST Yield loss: due to increased chip area or more chips in system Yield loss: due to increased chip area or more chips in system

because of BIST

Reliability reduction: due to increased area

Reliability reduction: due to increased area

Increased BIST hardware complexity: happens when BIST

hardware is made testable

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BIST Benefits

Faults tested:

Single combinational/sequential stuck-at faults Single combinational/sequential stuck at faults Delay faults Single stuck-at faults in BIST hardware Single stuck-at faults in BIST hardware

BIST benefits

Reduced testing and maintenance cost Reduced testing and maintenance cost Lower test generation cost Reduced storage/maintenance of test patterns Reduced storage/maintenance of test patterns Simpler and less expensive ATE Can test many units in parallel Can test many units in parallel Shorter test application times C

t t t f ti l t p d

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Can test at functional system speed

Definitions

BILBO – Built-in logic block observer, extra hardware added to

flip-flops so they can be reconfigured as an LFSR pattern generator or response compacter, a scan chain, or as flip-flops

Concurrent testing – Testing process that detects faults during Concurrent testing – Testing process that detects faults during

normal system operation

CUT – Circuit-under-test Exhaustive testing – Apply all possible 2n patterns to a circuit

with n inputs d bl l l

Irreducible polynomial – Boolean polynomial that cannot be

factored

LFSR

Linear feedback shift register hardware that generates

LFSR – Linear feedback shift register, hardware that generates

pseudo-random pattern sequence

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More Definitions

Primitive polynomial – Boolean polynomial p (x) that can

be used to compute increasing powers n of xn modulo p(x) p g p p( ) to obtain all possible non-zero polynomials of degree less than p (x) P d h i i B k i i i ll

Pseudo-exhaustive testing – Break circuit into small,

• verlapping blocks and test each exhaustively

Pseudo-random testing – Algorithmic pattern generator that Pseudo random testing

Algorithmic pattern generator that produces a subset of all possible tests with most of the properties of randomly-generated patterns

Signature – Any statistical circuit property distinguishing

between bad and good circuits

TPG

H rd r test pattern generator

TPG – Hardware test pattern generator

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BIST Process

Test controller – Hardware that activates self-test simultaneously on all PCBs Each board controller activates parallel chip BIST Each board controller activates parallel chip BIST Diagnosis effective only if very high fault coverage

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BIST Architecture BIST Architecture

Note: BIST cannot test the following wires and transistors:

From PI pins to Input MUX From PI pins to Input MUX From POs to output pins

⇒ High-speed ATE or boundary scan required for these paths

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⇒ High-speed ATE or boundary scan required for these paths.

BILBO – Works as Both a PG and a RC

Built-in Logic Block Observer (BILBO) -- 4 modes:

• 1. Flip-flop
• 2. LFSR pattern generator
• 3. LFSR response compacter

4

S h i f fli fl

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• 4. Scan chain for flip-flops

Complex BIST Architecture Complex BIST Architecture

Testing epoch I:

LFSR1 generates tests for CUT1 and CUT2 BILBO2 (LFSR3) compacts CUT1 (CUT2)

Testing epoch II:

BILBO2 generates test patterns for CUT3

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LFSR3 compacts CUT3 response

Bus-Based BIST Architecture Bus-Based BIST Architecture

Self-test control broadcasts patterns to each CUT over bus –

parallel pattern generation

Awaits bus transactions showing CUT’s responses to the

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patterns: serialized compaction

Pattern Generation Pattern Generation

Store in ROM – too expensive in chip area Store in ROM too expensive in chip area Exhaustive Pseudo-exhaustive Pseudo-random (LFSR) – Preferred method Binary counters – use more hardware than LFSR Test pattern augmentation

LFSR combined with a few patterns in ROM Hardware diffracter – generates pattern cluster in neighborhood of pattern stored in ROM

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Exhaustive Pattern Generation Exhaustive Pattern Generation

Sho s that e er state and transition

• rks

Shows that every state and transition works For n-input circuits, requires all 2n vectors I

ti l f > 20

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Impractical for n > 20

Pseudo-Exhaustive Method

Partition large circuit

into fanin cones into fanin cones Backtrace from each PO to PIs influencing it Test fanin cones in parallel (if possible) to reduce time

Reduced # of tests from 28 = 256 to 25 x 2 = 64 Reduced # of tests from 2

256 to 2 x 2 64

Incomplete fault coverage (if test pattern length is shortened

from exhaustive in one of two test modes)

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)

Random Pattern Testing

Bottom curve: Bottom curve: Random- Pattern Resistant circuit Resistant circuit

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Pseudo-Random Pattern Generation

Standard (Type-I, External) Linear Feedback Shift Register

( S ) (LFSR) Produces patterns algorithmically – repeatable H t f d i bl d b ti Has most of desirable random number properties

Need not cover all 2n input combinations Long sequences needed for good fault coverage

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Long sequences needed for good fault coverage

Matrix Equation for Standard LFSR Matrix Equation for Standard LFSR

X0 (t + 1) 1 … X0 (t)

0 (

) X1 (t + 1) . . . . . 1 . . . . . … . . . . . .

0 ( )

X1 (t) . . . = . Xn-3 (t + 1) Xn-2 (t + 1) . . . … … . 1 . 1 . Xn-3 (t) Xn-2 (t) = Xn-1 (t + 1) h1 h2 1 … hn-2 hn-1 Xn-1 (t) X (t + 1) = Ts X (t) (Ts is companion matrix)

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LFSR I l t G l i Fi ld LFSR Implements a Galois Field

Galois field (mathematical system):

Multiplication by x same as right shift of LFSR Addition operator is XOR

Ts companion matrix:

1st column 0 except nth element which is always 1 (X 1 column 0, except nth element which is always 1 (X0 always feeds Xn-1) Rest of row n – feedback coefficients hi Rest is identity matrix I – means a right shift

Near-exhaustive (maximal length) LFSR

Cycles through 2n – 1 states (excluding all-0) 1 pattern of n 1’s, one of n-1 consecutive 0’s

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Standard n-Stage LFSR Implementation g p

Autocorrelation: an shifted seq ence same as original in Autocorrelation: any shifted sequence same as original in

2n-1 – 1 bit positions, differs in 2n-1 positions

If hi = 0 that XOR gate is deleted

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If hi = 0, that XOR gate is deleted

LFSR Theory

Cannot initialize to all 0’s– hangs Cannot initialize to all 0 s hangs If X is initial state, progresses through states X, Ts X,

T 2 X T 3 X Ts

2 X, Ts 3 X, …

Matrix period:

k

Smallest k such that Ts

k = I

k LFSR cycle length

≡

y g

Described by characteristic polynomial:

f (x) = |T I X | f (x) = |Ts – I X | = 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn

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Example External XOR LFSR Example External XOR LFSR

Characteristic polynomial f (x) = 1 + x + x3

(read taps from right to left)

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( p g )

External XOR LFSR External XOR LFSR

Pattern sequence for example LFSR (previous slide):

X0 1 1 1 1 1 1 1 1 1 1 X1 X2 1 1 1 1 1 1 1 1 1 …

Always have 1 and xn terms in polynomial

N LFSR h 1 i i

Never repeat an LFSR pattern more than 1 time; repeating same

error vector cancels fault effect X (t + + 1) 0 1 0 X (t) X0 (t + + 1) X1 (t (t + 1) + 1) X2 (t + 1) 1 1 1 1 X0 (t) X1 (t) (t) X2 (t) =

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X2 (t 1) 1 1 0 X2 (t)

Generic Modular (Internal, Type-II) LFSR Generic Modular (Internal, Type II) LFSR

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Modular Internal XOR LFSR

Described by companion matrix Tm = Ts

T

I l XOR LFSR XOR i b D fli fl

Internal XOR LFSR – XOR gates in between D flip-flops Equivalent to standard External XOR LFSR

d ff With a different state assignment Faster – usually does not matter Same amount of hardware

X (t + 1) = Tm X (t) f (x) = |Tm – I X |

= 1 + h1 x + h2 x2 + … + hn-1 xn-1 + xn

Right shift – equivalent to multiplying by x, and then

dividing by characteristic polynomial and storing the r ind r

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remainder

Modular LFSR Matrix

X 1 X X0 (t + 1) X1 (t + 1) X (t + 1) 1 1 … … 1 h1 h X0 (t) X1 (t) X (t) X2 (t + 1) . . . X (t + 1) 1 . . . . . . . . . … . . . h2 . . . h X2 (t) . . . X (t) = . . . Xn-3 (t + 1) Xn-2 (t + 1) Xn 1 (t + 1) 1 … … … 1 hn-3 hn-2 hn 1 Xn-3 (t) Xn-2 (t) Xn 1 (t) Xn-1 (t 1) … 1 hn-1 Xn-1 (t)

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Example Modular LFSR Example Modular LFSR

f

2 7 8

f (x) = 1 + x2 + x7 + x8 Read LFSR tap coefficients from left to right

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Response Compaction Response Compaction

Severe amounts of data in CUT response to LFSR patterns.

example: p Generate 5 million random patterns CUT has 200 outputs p Leads to: 5 million x 200 = 1 billion bits response

Uneconomical to store and check all of these responses on

p chip

Responses must be compacted

p p

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Definitions Definitions

Aliasing – Due to information loss, signatures of good and

g , g g some bad machines match

Compaction – Drastically reduce # bits in original circuit

l i f i response – lose information

Compression – Reduce # bits in original circuit response –

no information loss – fully invertible (can get back original no information loss fully invertible (can get back original response)

Signature analysis – Compact good machine response into

d h good machine signature. Actual signature generated during testing, and compared with good machine signature

Transition Count Response Compaction: Count number of Transition Count Response Compaction: Count number of

transitions from 0 1 and 1 0 as a signature

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Transition Counting

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Transition Counting Details Transition Counting Details

Transition count:

C R

m

C (R) = Σ (ri ri-1) for all m primary outputs

To maximize fault coverage: i = 1

⊕

g Make C (R0) (good machine transition count) as large or as small as possible p

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LFSR for Response Compaction p p

Use cyclic redundancy check code (CRCC) generator (LFSR)

for response compacter

Treat data bits from circuit POs to be compacted as a

d i d ffi i l i l decreasing order coefficient polynomial

CRCC divides the PO polynomial by its characteristic

l i l polynomial Leaves remainder of division in LFSR M i i i li LFSR d l ( ll 0) b f Must initialize LFSR to seed value (usually 0) before testing

After testing

compare signature in LFSR to known good

After testing – compare signature in LFSR to known good

machine signature

Critical: Must compute good machine signature

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Critical: Must compute good machine signature

Example Modular LFSR Response Compacter

LFSR seed value is “00000”

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Polynomial Division

Inputs Inputs Initial Sta Initial State X0 X1 X2 X3 X4 Initial Sta Initial State 1 1 1 1 1 1 1 1 Lo Logic gic Sim Simula lation: tion: 1 1 1 1 1 1 1 1 1 Logic simulation: Remainder = 1 + x2 + x3 1 1 1 1 1 1 1 Logic simulation: Remainder = 1 + x + x 0 1 0 1 0 0 0 1 0 x0 + 1 x1 + 0 x2 + 1 x3 + 0 x4 + 0 x5 + 0 x6 + 1 x7

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0.x + 1.x + 0.x + 1.x + 0.x + 0.x + 0.x + 1.x

Symbolic Polynomial Division y y

x2 x7 + 1 + x3 + x x5 + x3 + x + 1 x7 + x5 x5 + x3 + x2 + x2 + x x + x + x + 1 x x5 + x3

3

+ x +

2

+ x + x + 1 1 remainder x3 + x2 + 1 remainder f Remainder matches that from logic simulation

• f the response compacter.

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Multiple-Input Signature Register p p g g (MISR)

Problem with ordinary LFSR response compacter:

Too much hardware if one of these is put on each primary

• utput (PO)

Solution: MISR – compacts all outputs into one LFSR

Works because LFSR is linear – obeys superposition principle Superimpose all responses in one LFSR – final remainder is XOR sum of remainders of polynomial divisions of each PO by the characteristic polynomial PO by the characteristic polynomial

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MISR Matrix Equation MISR Matrix Equation

d (t)

• tp t re pon e on PO

t time t

di (t) – output response on POi at time t

X0 (t + + 1) 1 … X0

0 (t)

d0

0 (t)

X0 (t + + 1) X1 (t (t + 1) + 1) . . 1 . . . . … … . . . . X0

0 (t)

X1

1 (t)

(t) . . d0

0 (t)

d1

1 (t)

(t) . . . Xn-3

n-3 (t

(t + 1) + 1) Xn-2 (t + t + 1) . . … … . 1 . 1 . Xn-3

n-3 (t)

(t) Xn-2

2 (t)

= . dn-3

n-3 (t)

(t) dn-2

2 (t)

+

n-2 (

) Xn-1

n-1 (t

(t + 1) 1) h1 1 … h … hn-2

n-2 hn-1 n-1 n-2 2 ( )

Xn-1

n-1 (t)

(t)

n-2 2 ( )

dn-1

n-1 (t)

(t)

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Modular MISR Example p

X0 (t + + 1) 1 X0

0 (t)

d0

0 (t)

X0 (t + + 1) X1 (t (t + 1) + 1) X2 (t + t + 1) 1 1 1 1 = X0

0 (t)

X1

1 (t)

(t) X2 (t) d0

0 (t)

d1

1 (t)

(t) d2 (t) +

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2 (

)

2 ( ) 2 ( )

Multiple Signature Checking Multiple Signature Checking

U

2 diff t t ti p h

Use 2 different testing epochs:

1st with MISR with 1 polynomial 2nd i h MISR i h diff l i l 2nd with MISR with different polynomial

Reduces probability of aliasing,

V lik l h b h l i l ill li f h Very unlikely that both polynomials will alias for the same fault

Lo

hard are cost:

Low hardware cost:

A few XOR gates for the 2nd MISR polynomial A 2 1 MUX t l t b t t f db k l i l A 2-1 MUX to select between two feedback polynomials

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Additional MISR Aliasing

MISR has more aliasing than LFSR on single PO

Error in CUT output dj at ti, followed by error in t t d t t li i t i t if

• utput dj+h at ti+h, eliminates any signature error if

no feedback tap in MISR between bits Qj and Qj+h.

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Experiment Hardware p

3 bit e ha sti e binar co nter for pattern generator 3 bit exhaustive binary counter for pattern generator

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Transition Counting vs. LFSR

LFSR aliases for f sa1, transition counter for a sa1

Pattern abc Good a sa1 f sa1 b sa1 Responses 000 001 010 1 1 1 1 1 1 010 011 100 101 1 1 1 1 1 1 1 1 1 1 101 110 111 1 1 1 1 1 1 1 1 1 1 1 1 Transition Count LFSR 3 001

Signatures

3 101 001 1 010

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LFSR 001 101 001 010

Built-in Logic Block Observer (BILBO) g ( )

Combined functionality of D flip-flop, pattern generator,

h response compacter, & scan chain Reset all FFs to 0 by scanning in zeros

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Example BILBO Usage p g

SI – Scan In SI

Scan In

SO – Scan Out Characteristic polynomial: 1 + x +

+ xn

Characteristic polynomial: 1 + x + … + x CUTs A and C: BILBO1 is MISR, BILBO2 is LFSR

CUT B BILBO1 i LFSR BILBO2 i MISR

CUT B: BILBO1 is LFSR, BILBO2 is MISR

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BILBO Serial Scan Mode

B1 B2 = “00” B1 B2 = 00 Dark lines show enabled data paths

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BILBO LFSR Pattern Generator Mode

B1 B2 = “01” B1 B2 = 01

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BILBO in D FF (Normal) Mode BILBO in D FF (Normal) Mode

B1 B2

“10”

B1 B2 = “10”

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BILBO in MISR Mode

B1 B2 = “11” B1 B2 = 11

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