hybrid tlb coal b coalescing i improving g tlb translati
play

Hybrid TLB Coal B Coalescing: I Improving g TLB Translati tion C - PowerPoint PPT Presentation

Feb 08, 2024 •306 likes •1.35k views

Hybrid TLB Coal B Coalescing: I Improving g TLB Translati tion C Cover erage e under er D Diver erse e Fr Fragm gmented M Mem emory A y Allocations Chang Hyun Park , Taekyung Heo, Jungi Jeong, and Jaehyuk Huh Introduction

  1. Past Proposals: : Direct Segments • Segment based translation [1] • Three values represent contiguous translation of any size • Fully assoc. lookup for multiple segments (limits size of TLB) • Redundant Memory Mappings (RMM) [6] -> 32 Fully-associative TLB Base Limit Virtual Pages Direct Segment Offset Base Limit Offset Physical Pages Direct Segment [1] Basu et al. ISCA ’13 51 [6] Karakostas et al. ISCA ‘15

  2. Past Proposals: : Direct Segments • Segment based translation [1] • Three values represent contiguous translation of any size • Fully assoc. lookup for multiple segments (limits size of TLB) • Redundant Memory Mappings (RMM) [6] -> 32 Fully-associative TLB Base Limit Virtual Pages Direct Segment Offset Base Limit Offset Physical Pages Direct Segment [1] Basu et al. ISCA ’13 52 [6] Karakostas et al. ISCA ‘15

  3. Past Proposals: : Direct Segments • Segment based translation [1] • Three values represent contiguous translation of any size • Fully assoc. lookup for multiple segments (limits size of TLB) • Redundant Memory Mappings (RMM) [6] -> 32 Fully-associative TLB Base Limit Virtual Pages Direct Segment Offset Base Limit Offset Physical Pages Direct Segment [1] Basu et al. ISCA ’13 53 [6] Karakostas et al. ISCA ‘15

  4. Past Proposals: : Direct Segments • Segment based translation [1] • Three values represent contiguous translation of any size • Fully assoc. lookup for multiple segments (limits size of TLB) • Redundant Memory Mappings (RMM) [6] -> 32 Fully-associative TLB Base Limit Efficient with small number of Virtual Pages Direct Segment big memory chunks Offset Base Limit Offset Physical Pages Direct Segment [1] Basu et al. ISCA ’13 54 [6] Karakostas et al. ISCA ‘15

  5. Past P Proposals: Summary • Large pages • Affinity for large pages (2MB) • Cluster TLB • Affinity for clustering of mapping of up to 8 pages • Segment translations • Affinity for small number of large chunks (32 entry TLB) 55

  6. Past P Proposals: Summary • Large pages • Affinity for large pages (2MB) • Cluster TLB • Affinity for clustering of mapping of up to 8 pages • Segment translations • Affinity for small number of large chunks (32 entry TLB) Prior proposals efficiently support specific memory mapping scenarios 56

  7. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity Node Node Node Node Node Node Node Node Regular Pages Large Page [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 57 [4] Agarwal et al. ASPLOS ‘17

  8. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 58 [4] Agarwal et al. ASPLOS ‘17

  9. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 59 [4] Agarwal et al. ASPLOS ‘17

  10. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 60 [4] Agarwal et al. ASPLOS ‘17

  11. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 61 [4] Agarwal et al. ASPLOS ‘17

  12. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 62 [4] Agarwal et al. ASPLOS ‘17

  13. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 63 [4] Agarwal et al. ASPLOS ‘17

  14. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 64 [4] Agarwal et al. ASPLOS ‘17

  15. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 65 [4] Agarwal et al. ASPLOS ‘17

  16. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 66 [4] Agarwal et al. ASPLOS ‘17

  17. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 67 [4] Agarwal et al. ASPLOS ‘17

  18. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 68 [4] Agarwal et al. ASPLOS ‘17

  19. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 69 [4] Agarwal et al. ASPLOS ‘17

  20. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 70 [4] Agarwal et al. ASPLOS ‘17

  21. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 71 [4] Agarwal et al. ASPLOS ‘17

  22. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 [3] Lee et al. ISCA ‘15 72 [4] Agarwal et al. ASPLOS ‘17

  23. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 Cold Pages [3] Lee et al. ISCA ‘15 73 [4] Agarwal et al. ASPLOS ‘17

  24. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 Hot Pages Cold Pages [3] Lee et al. ISCA ‘15 74 [4] Agarwal et al. ASPLOS ‘17

  25. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 Hot Pages Cold Pages [3] Lee et al. ISCA ‘15 75 [4] Agarwal et al. ASPLOS ‘17

  26. Large C La Conti tiguity vs. Memor ory Non Non-Uniform rmity • Conflicting goals of NUMA systems and large pages [2] • Memory traffic balance vs. efficient address translation Node Node Node Node Different systems have different memory mapping needs Node Node Node Node Regular Pages Large Page • Heterogeneous memory worsens non-uniformity [3][4] [2] Baptiste et al. ATC ’ 14 Hot Pages Cold Pages [3] Lee et al. ISCA ‘15 76 [4] Agarwal et al. ASPLOS ‘17

  27. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] 77 [7] Kwon et al. OSDI ’16

  28. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] CDF of process memory 78 [7] Kwon et al. OSDI ’16

  29. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] CDF of process memory Well suited for Cluster 79 [7] Kwon et al. OSDI ’16

  30. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] Well suited for Large pages CDF of process memory Well suited for Cluster 80 [7] Kwon et al. OSDI ’16

  31. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] Well suited for Large pages CDF of process memory Well suited for Cluster Well suited for ?? 81 [7] Kwon et al. OSDI ’16

  32. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] Well suited for Large pages CDF of process memory Well suited for Cluster Well suited for ?? 82 [7] Kwon et al. OSDI ’16

  33. Need f for a r an Al All-Roun unde der Solution • Contiguity distribution varies among workloads • Also varies within the same workload [7] Well suited for Large pages CDF of process memory Well suited for Cluster Well suited for ?? Can we make a TLB scheme that works well for diverse scenarios? 83 [7] Kwon et al. OSDI ’16

  34. Hyb ybrid T TLB LB C Coalesci cing Hardware TLB Operating System Page Table 84

  35. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 85

  36. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 86

  37. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 87

  38. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 88

  39. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 89

  40. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 90

  41. Hyb ybrid T TLB LB C Coalesci cing Hardware We propose a TLB with TLB TLB adjustable coverage • HW - SW Joint Effort • HW offers adjustable TLB coverage • Number of TLB entries fixed • Coverage of entry adjustable Operating System • OS decides best TLB coverage • Adjusts TLB coverage per process • OS identifies contiguous chunks Page Table • Marks onto process page table 91

  42. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 8 Page Table 92

  43. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 4 Anchor Distance = 8 Page Table 93

  44. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 4 Anchor Distance = 8 Page Table 94

  45. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 4 Anchor Distance = 8 Page Table 95

  46. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 4 Anchor Distance = 8 Page Table 96

  47. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 4 Anchor Distance = 8 Page Table 97

  48. Anch nchor • Anchors are special entries in the page table • Placed at every alignments of anchor distance • Anchor distance is a power of 2 (for encoding efficiency) • Anchor distance configurable by OS Anchor Distance = 4 Anchor Distance = 8 Page Table 98

  49. Anchor An r Page Table • Uses the Page Table • Anchor covers up to distance(4) contiguous pages • Each anchor represents contiguity that begins at anchor • OS marks contiguity onto the anchor page table Virtual Pages 2 3 4 1 4 Anchor Mappings Regular Mappings Physical Pages 99

  50. Anchor An r Page Table • Uses the Page Table • Anchor covers up to distance(4) contiguous pages • Each anchor represents contiguity that begins at anchor • OS marks contiguity onto the anchor page table Virtual Pages 2 3 4 1 4 Anchor Mappings Regular Mappings Physical Pages 100

  51. Anchor An r Page Table • Uses the Page Table • Anchor covers up to distance(4) contiguous pages • Each anchor represents contiguity that begins at anchor • OS marks contiguity onto the anchor page table Virtual Pages 2 3 4 1 4 Anchor Mappings Regular Mappings Physical Pages 101

  52. An Anchor r TLB • Integrated into the L2 TLB • L1 keeps regular entries • Caches both regular and anchor page table entries • Regular and anchor indexed differently Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 TLB Entries 0 | 2 0 | 3 0 | 4 1 | 4 3 | X Anchor Entry 3 | X Tag | Contiguity 3 | X Regular Entry 102

  53. An Anchor r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 3 | X Anchor Entry Regular Entry 103

  54. An Anchor r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 3 | X Anchor Entry Regular Entry 104

  55. An Anchor r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 0 | 3 3 | X Anchor Entry Regular Entry 105

  56. An Anchor r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 0 | 3 3 | X Anchor Entry Regular Entry 106

  57. Anchor An r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 0 | 3 3 | X Offset (2) < Anchor Entry Contiguity (3) Regular Entry 107

  58. Anchor An r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 0 | 3 3 | X Offset (2) < Anchor Entry Contiguity (3) Regular Entry HIT 108 return Anchor PFN + offset

  59. An Anchor r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 0 | 3 3 | X Offset (2) < MISS Anchor Entry Contiguity (3) Start Page Walk Regular Entry HIT 109 return Anchor PFN + offset

  60. An Anchor r TLB Lookup • On L1 TLB Miss Anchor TLB looks up • Regular TLB first • Anchor TLB next Anchor TLB (4 sets) Virtual Pages 2 3 4 0 4 0 | 2 1 | 4 0 | 3 3 | X 0 | 4 3 | X 0 | 3 3 | X Offset (2) < MISS Anchor Entry Contiguity (3) Start Page Walk Regular Entry HIT 110 return Anchor PFN + offset

  61. Operati ting S System Responsibilities • OS periodically selects process anchor distance • Heuristic algorithm to minimize TLB entry count • OS adjusts anchor distance • Anchor distance based on selection algorithm • OS marks mapping contiguity • Memory mapping contiguity in anchor page table entry 111

  62. Simulation on M Met ethodol ology • Trace based TLB simulator (Based on Intel Haswell) TLB Configuration Common L1 4KB: 64 entry, 4 way 2MB: 32 entry, 4 way Baseline L2 / THP 4KB/2MB: 1024 entry, 8 way Cluster Regular (4KB/2MB): 768 entry, 6 way Cluster-8: 320 entry, 5 way RMM (Multiple segments) Baseline L2 TLB + RMM: 32 entry, fully-assoc. Anchor (Selected/Static 4KB/2MB/anchor: 1024 entry, 8 way Ideal) 112

  63. Memory Mapping Scenarios • Two class of memory mapping scenarios • Two real system memory mappings • Four synthetic memory mappings Name Trace information demand Default Linux memory mapping eager ‘Eager’ allocation low 1– 16 pages (4KB – 64KB) medium 1 – 512 pages (4KB – 2MB) high 512 – 64K pages (2MB – 256MB) max Maximum contiguity 113

  64. Evaluati tion – TLB LB M Misses of demand mappi ping ng 100 90 Relative TLB Misses (%) 80 70 60 50 40 30 20 10 0 THP Cluster RMM Anchor Selected Anchor Ideal 114

  65. Evaluati tion – TLB LB M Misses of demand mappi ping ng 100 90 Relative TLB Misses (%) 80 70 60 50 40 30 20 10 0 THP Cluster RMM Anchor Selected Anchor Ideal 115

  66. Evaluati tion – TLB LB M Misses of demand mappi ping ng 100 90 Relative TLB Misses (%) 80 70 60 50 40 30 20 10 0 THP Cluster RMM Anchor Selected Anchor Ideal 116

  67. Evaluati tion – TLB LB M Misses of demand mappi ping ng 100 90 Relative TLB Misses (%) 80 70 60 50 40 30 20 10 0 Anchor TLB adjusted to satisfy small contiguities THP Cluster RMM Anchor Selected Anchor Ideal 117

  68. Evaluati tion – TLB LB M Misses of medium mappi ping 100 90 Relative TLB Misses (%) 80 70 60 50 40 30 20 10 0 THP Cluster RMM Anchor Selected Anchor Ideal 118

  69. Evaluati tion – TLB LB M Misses of medium mappi ping 100 90 Relative TLB Misses (%) 80 70 60 50 40 30 20 10 0 Anchor adjusted coverage to provide best TLB reduction THP Cluster RMM Anchor Selected Anchor Ideal 119

  70. Evaluati tion – TLB M Misses of all mappi ping ng 100 90 80 Relative TLB Misses (%) 70 60 50 40 30 20 10 0 demand eager low cont. med cont. high cont. max cont. Baseline THP Cluster RMM Anchor Selected Anchor Ideal 120

Download Presentation
Download Policy: The content available on the website is offered to you 'AS IS' for your personal information and use only. It cannot be commercialized, licensed, or distributed on other websites without prior consent from the author. To download a presentation, simply click this link. If you encounter any difficulties during the download process, it's possible that the publisher has removed the file from their server.

Recommend

Control Flow Coalescing on a Hybrid Dataflow/von Neumann GPGPU Dani Voitsechov Yoav Etsion

Control Flow Coalescing on a Hybrid Dataflow/von Neumann GPGPU Dani Voitsechov Yoav Etsion

Control Flow Coalescing on a Hybrid Dataflow/von Neumann GPGPU Dani Voitsechov Yoav Etsion Technion - Israel Institute of Technology Electrical Engineering and Computer Science Departments Massively Parallel Computing Massively

466 views • 27 slides
On the Complexity of Register Coalescing F . Bouchez, A. Darte, and F . Rastello LIP UMR CNRS

On the Complexity of Register Coalescing F . Bouchez, A. Darte, and F . Rastello LIP UMR CNRS

Coalescing On the Complexity of Register Coalescing F . Bouchez, A. Darte, and F . Rastello LIP UMR CNRS Inria ENS Lyon UCBL France CGO07, San Jose Coalescing Outline What, Why, and How to Coalesce 1 Basic Formulation The

1.32k views • 85 slides
Improving Offset Assignment through Simultaneous Variable Coalescing Desiree Ottoni, Guido Araujo

Improving Offset Assignment through Simultaneous Variable Coalescing Desiree Ottoni, Guido Araujo

7th International Workshop on Software and Compilers for Embedded Systems - SCOPES 2003 Improving Offset Assignment through Simultaneous Variable Coalescing Desiree Ottoni, Guido Araujo {desiree.ottoni | guido}@ic.unicamp.br Guilherme Ottoni

270 views • 12 slides
Hybrid Corporate Social Responsibility(CSR) Funding Model WESTERN COALFIELDS LIMITED (A

Hybrid Corporate Social Responsibility(CSR) Funding Model WESTERN COALFIELDS LIMITED (A

Hybrid Corporate Social Responsibility(CSR) Funding Model WESTERN COALFIELDS LIMITED (A subsidiary of Coal India Limited) INTRODUCTION Hybrid Water Cooperatives Western Coalfields Limited - Coal Producing subsidiary of Coal India

116 views • 8 slides
Integer Set Coalescing Sven Verdoolaege INRIA and KU Leuven January 19, 2015 January 19, 2015

Integer Set Coalescing Sven Verdoolaege INRIA and KU Leuven January 19, 2015 January 19, 2015

January 19, 2015 1 / 27 Integer Set Coalescing Sven Verdoolaege INRIA and KU Leuven January 19, 2015 January 19, 2015 2 / 27 Outline Introduction and Motivation 1 Polyhedal Model The need for coalescing Traditional Coalescing

1.24k views • 107 slides
Eulerian Multi-Fluid models for the description of polydisperse coalescing sprays : evaluation of

Eulerian Multi-Fluid models for the description of polydisperse coalescing sprays : evaluation of

Eulerian Multi-Fluid models for the description of polydisperse coalescing sprays : evaluation of various numerical strategies F. Doisneau, F. Laurent Context Coalescing sprays Astrophysics Meteorology (planets, nebulae) (raindrops,

562 views • 19 slides
Lecture 6.2 Performance Considerations Memory Coalescing in CUDA Objective To learn that

Lecture 6.2 Performance Considerations Memory Coalescing in CUDA Objective To learn that

GPU Teaching Kit Accelerated Computing Lecture 6.2 Performance Considerations Memory Coalescing in CUDA Objective To learn that memory coalescing is important for effectively utilizing memory bandwidth in CUDA Its origin in DRAM

623 views • 13 slides
COAL COVER COAL COAL COAL COVER COVER COVER Searfoss

COAL COVER COAL COAL COAL COVER COVER COVER Searfoss

Searfoss Enterprises COAL COVER COAL COAL COAL COVER COVER COVER Searfoss Enterprises Coal Cover Automated Retractable Hard Top * Does not protrude past the perimeter of the coal car anywhere. *

627 views • 17 slides
Australias Coal and Clean Coal Industries Josh Cosgrave A/g General Manager Coal and

Australias Coal and Clean Coal Industries Josh Cosgrave A/g General Manager Coal and

Australias Coal and Clean Coal Industries Josh Cosgrave A/g General Manager Coal and Minerals Productivity Branch 7 September 2016 Australias coal industry Major global producer and exporter Australias thermal coal costs of

366 views • 12 slides
B.C. and Canada Michelle Mondeville Director of Communications and Stakeholder Relations, Coal

B.C. and Canada Michelle Mondeville Director of Communications and Stakeholder Relations, Coal

The Economic Importance of the Coal Industry in B.C. and Canada Michelle Mondeville Director of Communications and Stakeholder Relations, Coal Association of Canada Canadian Coal Mines 2 Coal Production (2011) Province Met. Coal Thermal Coal

463 views • 20 slides
Typical 500 MW Coal Fired Plant Selective Catalytic Reduction (SCR) Boiler Electrostatic

Typical 500 MW Coal Fired Plant Selective Catalytic Reduction (SCR) Boiler Electrostatic

COAL GEN PRESENTATION Efficiency Improvements to the Existing Coal-Fueled Fleet August 12, 2010 Richard F. Storm The average pulverized coal units in America are about as old - as I have been involved as an adult engineer in this business

167 views • 14 slides
Improving Reliability of Platooning Control Messages Using Radio and Visible Light Hybrid

Improving Reliability of Platooning Control Messages Using Radio and Visible Light Hybrid

Improving Reliability of Platooning Control Messages Using Radio and Visible Light Hybrid Communication Susumu Ishihara (Shizuoka University) Vince Rabsatt, Mario Gerla (UCLA) To the direct follower Leader to followers Platooning Camera/

495 views • 22 slides
Interrupt Coalescing in Xen with Scheduler Awareness Michael Peirce &amp; Kevin Boos Outline

Interrupt Coalescing in Xen with Scheduler Awareness Michael Peirce &amp; Kevin Boos Outline

Interrupt Coalescing in Xen with Scheduler Awareness Michael Peirce &amp; Kevin Boos Outline Background Hypothesis vIC-style Interrupt Coalescing Adding Scheduler Awareness Evaluation 2 Background Xen split block

717 views • 32 slides
PARSEME WG 3 Improving PP attachment in a hybrid dependency parser using semantic,

PARSEME WG 3 Improving PP attachment in a hybrid dependency parser using semantic,

Gerold Schneider: PARSEME WG 3 1 PARSEME WG 3 Improving PP attachment in a hybrid dependency parser using semantic, distributional, and lexical resources EU COST Intitiative Meeting Athens, Greece, March 11-12 Dr. Gerold Schneider Institute

310 views • 4 slides
Packet Coalescing for Dual-Mode Energy Efficient Ethernet: A Simulation Study Mehrgan Mostowfi

Packet Coalescing for Dual-Mode Energy Efficient Ethernet: A Simulation Study Mehrgan Mostowfi

Packet Coalescing for Dual-Mode Energy Efficient Ethernet: A Simulation Study Mehrgan Mostowfi School of Mathematical Sciences University of Northern Colorado Greeley, Colorado, USA mehrgan.mostowfi@unco.edu Slide 1 of 11 Packet Coalescing for

254 views • 11 slides
vIC: Interrupt Coalescing for Virtual Machine Storage Device IO

vIC: Interrupt Coalescing for Virtual Machine Storage Device IO

vIC: Interrupt Coalescing for Virtual Machine Storage Device IO Irfan Ahmad Ajay Gula@, Ali Mash@zadeh USENIX Annual Technical Conference June 15, 2011

630 views • 23 slides
#2: Graphics Part 2 SAMS SENIOR NON-CS TRACK Logistics - Memory bug fixed! - Workshop

#2: Graphics Part 2 SAMS SENIOR NON-CS TRACK Logistics - Memory bug fixed! - Workshop

#2: Graphics Part 2 SAMS SENIOR NON-CS TRACK Logistics - Memory bug fixed! - Workshop expectations - Office Hours- times, locations, OHQueue - Saving work between computers- Autolab download Last Time Recognize how a computer makes images

974 views • 20 slides
Heb. 6:19, This hope we have as an anchor of the soul, both sure and steadfast, and which

Heb. 6:19, This hope we have as an anchor of the soul, both sure and steadfast, and which

Heb. 6:19, This hope we have as an anchor of the soul, both sure and steadfast, and which enters the Presence behind the veil, Heb. 6:20, where the forerunner has entered for us, even Jesus, having become High Priest forever according

445 views • 17 slides
10. Learning to Rank Outline 10.1. Why Learning to Rank (LeToR)? 10.2. Pointwise, Pairwise,

10. Learning to Rank Outline 10.1. Why Learning to Rank (LeToR)? 10.2. Pointwise, Pairwise,

10. Learning to Rank Outline 10.1. Why Learning to Rank (LeToR)? 10.2. Pointwise, Pairwise, Listwise 10.3. Gathering User Input 10.4. LeToR Evaluation 10.5. Beyond Search Advanced Topics in Information Retrieval / Learning to Rank 2 10.1.

1.01k views • 34 slides
Loco Positioning An Open Source Local Positioning System FOSDEM 2017 Arnaud Taffanel Bitcraze

Loco Positioning An Open Source Local Positioning System FOSDEM 2017 Arnaud Taffanel Bitcraze

Loco Positioning An Open Source Local Positioning System FOSDEM 2017 Arnaud Taffanel Bitcraze AB Crazyflie 2.0 Open source flying development platform Designed to be expandable in both software and hardware 168MHz Cortex-M4 CPU

707 views • 32 slides
s Guided: Students repeat process with their own writing. Model: Circle the 3 ideas

s Guided: Students repeat process with their own writing. Model: Circle the 3 ideas

Week Anchor Lesson: Getting to 1 Feelings and Emotions through Pre-Writing Model: Brainstorm, What does Conne Belonging mean to me? ct Guided: Students generate their own personal brainstorm. Model: Respond

808 views • 24 slides
UC SF The Short Neck: What is the Role of Anchors, Chimneys, Z-Fen? Jade S. Hiramoto, MD, MAS

UC SF The Short Neck: What is the Role of Anchors, Chimneys, Z-Fen? Jade S. Hiramoto, MD, MAS

UC SF The Short Neck: What is the Role of Anchors, Chimneys, Z-Fen? Jade S. Hiramoto, MD, MAS UCSF Vascular Symposium April 4, 2019 VASCULAR SURGERY UC SAN FRANCISCO 1 UC SF Disclosures Research support and royalties from Cook,

333 views • 16 slides
Feature Selection Matters for Anchor-Free Object Detection Chenchen Zhu Carnegie Mellon

Feature Selection Matters for Anchor-Free Object Detection Chenchen Zhu Carnegie Mellon

Carnegie Mellon Feature Selection Matters for Anchor-Free Object Detection Chenchen Zhu Carnegie Mellon University 04/29/2020 Carnegie Mellon Overview Background Motivation Feature Selection in Anchor-Free Detection General

466 views • 42 slides
EE 6882 Statistical Methods for Video Indexing and Analysis Fall 2003 Prof. Shih-Fu Chang

EE 6882 Statistical Methods for Video Indexing and Analysis Fall 2003 Prof. Shih-Fu Chang

EE 6882 Statistical Methods for Video Indexing and Analysis Fall 2003 Prof. Shih-Fu Chang http://www.ee.columbia.edu/~sfchang Lecture 1 (9/3/03) 1 Research Problems in Video Indexing and Analysis Object detection and recognition (e.g.,

644 views • 27 slides

More recommend