branch prediction 1 last time what happens with TLB in access - PowerPoint PPT Presentation

branch prediction 1

last time what happens with TLB in access patterns overlapping TLB and cache index lookup overview of caches and page table lookups and TLB generally 3

an OOO pipeline combined with register-ready info to issue instructions pt 2 load store write back commit branch prediction needs to happen before instructions decoded done with cache-like tables of information about recent branches register renaming done here stage needs to keep mapping from architectural to physical names instruction queue holds pending renamed instructions (issue = start executing) ALU read from much larger register fjle and handle forwarding register fjle: typically read 6+ registers at a time (extra data paths wires for forwarding not shown) many execution units actually do math or memory load/store some may have multiple pipeline stages some may take variable time (data cache, integer divide, …) writeback results to physical registers register fjle: typically support writing 3+ registers at a time new commit (sometimes retire ) stage fjnalizes instruction fjgures out when physical registers can be reused again commit stage also handles branch misprediction reorder bufger tracks enough information to undo mispredicted instrs. 3 pt 1 register instr. fjle reorder bufger instr. cache branch predict decode more branch predict rename queue(s) 3 reg. ready info register read and forward ALU 1 ALU 2 ALU 4

done? mispred? num. PC 0x1233 %rbx / %x23 0x1239 %rax / %x30 0x1242 %rcx / %x31 0x1244 %rcx / %x32 0x1248 %rdx / %x34 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 0x129f %rax / %x12 but not fully fjnished new entries created on rename (not enough space? stall rename stage) 20 21 next renamed instruction goes in next slot, etc. (both architectural and physical versions) … remember at least its destination register … place newly started instruction at end of bufger … … … reorder bufger contains instructions started, 31 add here on rename remove here when committed add here on rename reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) reorder bufger (ROB) reorder bufger: on rename 19 … reg phys. reg %rax %x12 %rcx %x17 %rbx %x13 %rdx %x07 … 5 18 for new instrs %x19 %x23 … … free list instr dest. reg 14 15 16 17 arch. phys → arch. reg

reorder bufger: on rename on rename 18 19 20 21 … … … … … 31 reorder bufger (ROB) add here remove here 17 when committed add here on rename reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) place newly started instruction at end of bufger remember at least its destination register (both architectural and physical versions) next renamed instruction goes in next slot, etc. arch. 5 %x23 … %rbx %x13 %rdx %x07 … … for new instrs %x19 16 %x12 … free list %rcx instr dest. reg %rax reg 14 phys. reg 15 %x17 phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x23 0x1239 %rax / %x30 0x1242 %rcx / %x31 0x1244 %rcx / %x32 0x1248 %rdx / %x34 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 0x129f %rax / %x12

reorder bufger: on rename on rename 18 19 20 21 … … … … … 31 reorder bufger (ROB) add here remove here 17 when committed add here on rename reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) place newly started instruction at end of bufger remember at least its destination register (both architectural and physical versions) next renamed instruction goes in next slot, etc. arch. 5 %x23 … %rbx %x13 %rdx %x07 … … for new instrs %x19 16 %x12 … free list %rcx instr dest. reg %rax reg 14 phys. reg 15 %x17 phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x23 0x1239 %rax / %x30 0x1242 %rcx / %x31 0x1244 %rcx / %x32 0x1248 %rdx / %x34 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 0x129f %rax / %x12

reorder bufger: on rename on rename 19 20 21 … … … … … 31 32 reorder bufger (ROB) add here remove here 17 when committed add here on rename reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) place newly started instruction at end of bufger remember at least its destination register (both architectural and physical versions) next renamed instruction goes in next slot, etc. arch. 18 5 %x17 %x13 %rdx %x07 %x19 … … for new instrs %x19 %x23 16 … %rcx … free list instr dest. reg %x12 14 %rax reg 15 phys. reg %rbx phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x23 0x1239 %rax / %x30 0x1242 %rcx / %x31 0x1244 %rcx / %x32 0x1248 %rdx / %x34 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 0x129f %rax / %x12 0x1230 %rdx / %x19

reorder bufger: on rename on rename 19 20 21 … … … … … 31 32 reorder bufger (ROB) add here remove here 17 when committed add here on rename reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) reorder bufger contains instructions started, but not fully fjnished new entries created on rename (not enough space? stall rename stage) place newly started instruction at end of bufger remember at least its destination register (both architectural and physical versions) next renamed instruction goes in next slot, etc. arch. 18 5 %x17 %x13 %rdx %x07 %x19 … … for new instrs %x19 %x23 16 … %rcx … free list instr dest. reg %x12 14 %rax reg 15 phys. reg %rbx phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x23 0x1239 %rax / %x30 0x1242 %rcx / %x31 0x1244 %rcx / %x32 0x1248 %rdx / %x34 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 0x129f %rax / %x12 0x1230 %rdx / %x19

reorder bufger: on commit remove here for committed instructions commit stage tracks architectural to physical register map but not removed from reorder bufger (‘committed’) yet when result is computed instructions marked done in reorder bufger when committed when committed update this register map and free register list remove here reorder bufger (ROB) 31 … … … … when next-to-commit instruction is done and remove instr. from reorder bufger arch. %x23 for committed arch. reg phys … … %x21 %rdx %rbx arch. %x28 %rcx %x30 %rax reg phys. reg … 21 6 %x13 %x13 %x19 for new instrs … … %x07 %x19 %rdx %rbx … %x17 %rcx %x12 %rax reg phys. reg … free list 20 15 19 18 17 instr 16 dest. reg 14 phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x24 0x1239 %rax / %x30 0x1242 %rcx / %x31 0x1244 %rcx / %x32 0x1248 %rdx / %x34 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 0x129f %rax / %x12

reorder bufger: on commit remove here commit stage tracks architectural to physical register map but not removed from reorder bufger (‘committed’) yet when result is computed instructions marked done in reorder bufger when committed remove here when committed reorder bufger (ROB) when next-to-commit instruction is done 31 … … … … … 21 for committed instructions update this register map and free register list 20 %x23 for committed arch. reg phys … … %x21 %rdx %rbx and remove instr. from reorder bufger %x28 %rcx %x30 %rax reg phys. reg arch. arch. 6 instr for new instrs %rax free list … … %x13 %x19 … %x12 … %x07 %x19 %rdx %x13 %rbx %x17 dest. reg %rcx 14 17 15 19 16 reg reg phys. 18 phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x24 0x1239 %rax / %x30 � 0x1242 %rcx / %x31 0x1244 %rcx / %x32 � 0x1248 %rdx / %x34 � 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 � 0x129f %rax / %x12

reorder bufger: on commit when committed commit stage tracks architectural to physical register map but not removed from reorder bufger (‘committed’) yet when result is computed instructions marked done in reorder bufger when committed remove here remove here when next-to-commit instruction is done reorder bufger (ROB) 31 … … … … … for committed instructions update this register map and free register list arch. %rbx for committed … … %x21 %rdx %x23 %x28 and remove instr. from reorder bufger %rcx %x30 %rax reg phys. reg arch. 21 20 19 %rdx … %x13 %x19 for new instrs … … %x07 %x19 %x13 free list %rbx %x17 %rcx %x12 %rax reg phys. reg … instr 6 dest. reg 18 14 17 15 16 phys → arch. reg num. PC done? mispred? 0x1233 %rbx / %x24 phys → arch. reg 0x1239 %rax / %x30 � 0x1242 %rcx / %x31 0x1244 %rcx / %x32 � 0x1248 %rdx / %x34 � 0x1249 %rax / %x38 0x1254 PC 0x1260 %rcx / %x17 � 0x129f %rax / %x12