HW/SW Design Space Exploration on the Production Cell Setup - - PowerPoint PPT Presentation

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HW/SW Design Space Exploration on the Production Cell Setup - - PowerPoint PPT Presentation

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HW/SW Design Space Exploration on the Production Cell Setup Communicating Process Architectures 2009, Formal Methods Week Eindhoven University of Technology, The Netherlands, 04-11-2009 Marcel A. Groothuis, Jan F. Broenink Control Engineering,

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SLIDE 1

HW/SW Design Space Exploration

  • n the Production Cell Setup

Communicating Process Architectures 2009, Formal Methods Week Eindhoven University of Technology, The Netherlands, 04-11-2009

Marcel A. Groothuis, Jan F. Broenink

Control Engineering, Department of Electrical Engineering, University of Twente, The Netherlands

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 2

Contents

  • Introduction
  • Goals & Challenges
  • Embedded Control Systems Software
  • Design Space Exploration
  • Test Case
  • Demonstration Setup: Production Cell System
  • 6 Embedded Control Systems Software implementations
  • Production Cell ECS Implementations
  • CPU implementations (4)
  • FPGA implementations (2)
  • Evaluation
  • Conclusions & Ongoing work
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 3

Introduction Goals & Challenges

  • Realization of Embedded Control System (ECS) software
  • For mechatronics & robotic applications
  • Design Methodology
  • Model-driven ECS software design
  • Dependable software
  • Supporting tool chain
  • ECS design challenges
  • Large design space
  • Heterogeneous nature
  • Special demands on the software
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 4

Introduction Embedded Control System

  • Essential Properties Embedded Control Software
  • Purpose: control physical systems
  • Dynamic behaviour of the physical system essential for SW
  • Dependability: Safety, Reliability
  • Embedded Control System (ECS) software
  • Layered structure
  • Real-time constraints with low-latency requirement
  • Combination of time-triggered & event driven parts
  • Multiple Models of Computation (MoC)
  • Multiple Modeling formalisms

Embedded software Actuators Sensors Physical process I/O hardware Power amplifier D/A A/D Filtering/ Scaling Physical system

Soft real-time Hard real-time Non real-time

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 5

Introduction Design Method ECS SW

  • Approach
  • Stepwise & local refinement
  • From models towards ECS code
  • Verification by simulation & model checking
  • Way of Working
  • Discrete Event
  • Abstract interactions concurrent actors
  • Interaction between different MoCs
  • Timing low-level behaviour
  • Continuous Time
  • Model & Understand Physical system

dynamics

  • Simplify model, derive the control laws
  • Interfaces & target
  • Add non-ideal components (AD, DA, PC)
  • Scaling/conversion factors
  • Integrate DE & CT into ECS SW

Mechatronic system ECS SW Realization

CT SW layers DE SW layers

Integration

Timing (real-) time Implementation Target details Implementation Interfaces DE - CT Interfaces Supervisory & Interaction model Control Law Design Physical System Modeling Top level Abstract SW layer model

Mechatronic system Mechatronic system ECS SW Realization ECS SW Realization

CT SW layers DE SW layers

Integration

CT SW layers DE SW layers CT SW layers DE SW layers

Integration

Timing (real-) time Timing (real-) time Timing (real-) time Implementation Target details Implementation Target details Implementation Target details Implementation Interfaces Implementation Interfaces Implementation Interfaces DE - CT Interfaces DE - CT Interfaces DE - CT Interfaces Supervisory & Interaction model Supervisory & Interaction model Supervisory & Interaction model Control Law Design Control Law Design Control Law Design Physical System Modeling Physical System Modeling Physical System Modeling Top level Abstract SW layer model Top level Abstract SW layer model Top level Abstract SW layer model

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 6

Introduction Design Space Exploration

  • Embedded Control System
  • Large Design Space
  • (Many) Design Choices
  • Restrict solution space
  • Smaller pyramid
  • Examples choices
  • Modelling formalisms

& languages

  • Operating System choice
  • Parallellism
  • Sequential –or-

Parallel solution resource usage

  • Architecture
  • CPU  FPGA, distributed central
  • Reachable solutions
  • Dependent on all choices

Level of detail Abstraction level

FPGA FPGA CPU CPU

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 7

Test Case Production Cell

Production cell demonstrator

  • Based on:
  • Stork Plastics Molding machine
  • Architecture:
  • CPU (ECS / FPGA programmer)
  • FPGA (digital I/O / ECS)
  • 6 Production Cell units
  • Action in the production process
  • Moulding, Extraction,

Transportation, Storage

  • Synchronize with neighbours
  • Deadlock possible on > 7 blocks

CPU / FPGA

Motor 150W Gearhead 43:1 Encoder Motor 150W Gearhead 43:1 Encoder Al

Extraction unit Moulder door Feeder unit Feeder belt Extraction belt Rotation unit

Motor 70W Gearhead 18:1 Encoder Motor 150W Gearhead 15:1 Encoder Magnet Motor 150W Gearhead 15:1 Encoder

= Sensor

Extraction buffer Moulding unit

= Block movement direction

IR block detection

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 8

Production Cell ECS implementations

  • Embedded Control System implementations
  • Different choices
  • And many more…

No

  • SystemCSP

G Yes FPGA Floating point gCSP Handel-C float F Yes FPGA Integer gCSP Handel-C int (CPA 2008) E Partial CPU Floating point gCSP QNX RTOS D Yes CPU Floating point Ptolemy II C Yes CPU Floating point POOSL B Yes CPU Floating point gCSP RTAI Linux A Realization Target Data type Name Nr. FPGA FPGA CPU CPU Architecture: Par | | Seq Tools:

  • gCSP, FDR2
  • 20-sim
  • POOSL
  • Ptolemy II

Formalisms:

  • CSP
  • CCS
  • Multi MoC

OS:

  • RTAI Linux
  • QNX
  • No OS
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 9

Contents

  • Introduction
  • Goals & Challenges
  • Embedded Control Systems Software
  • Design Space Exploration
  • Test Case
  • Demonstration Setup: Production Cell System
  • 6 Embedded Control Systems Software implementations
  • Production Cell ECS Implementations
  • CPU implementations (4)
  • FPGA implementations (2)
  • Evaluation
  • Conclusions & Ongoing work
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 10

CPU gCSP RTAI (A)

  • Focus: proof of concept gCSP
  • Proof of concept gCSP for Embedded Control Systems software
  • Combination of untimed CSP and real-time Linux
  • Realization
  • Bottom up
  • 6 Semi-independent units  6 PARs
  • PRIPAR for real-time

levels

  • Periodic timing
  • TimerChannels
  • ECS SW  Environment
  • Rendezvous with OS

timer

  • Formal check with FDR2
  • Generated code from
  • gCSP + 20-sim
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 11

CPU gCSP RTAI (A)

  • Results
  • gCSP and CSP are usable for ECS software
  • Graphical process & channel structured
  • Graphical Finite State Machine diagram support wanted
  • Debugging CSP processes difficult (textual)  gCSP animation CPA2008
  • Formal verified process/channel structure (CSPm  FDR2)
  • Real-time behaviour gCSP code + CTC++ library + RTAI Linux
  • Missed deadlines; large process switch overhead; high CPU load
  • Challenge: Discrete Event CSP + Time Triggered loop control
  • Improvements
  • Timing implementation
  • CSP scheduling v.s. hard deadlines  QNX RTOS version CT library
  • Modeling
  • Diagram structure, Interaction, Hierarchy
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 12

CPU POOSL (B)

  • POOSL = Parallel Object Oriented Specification Language TU/e
  • CCS + Timing extension
  • Modeling high level behaviour Embedded Systems
  • Focus
  • Test timing
  • Integration DE & CT
  • Structured modeling
  • Concurrency & Interaction
  • DECT interfacing
  • Timing
  • Realization
  • Top-down
  • No formal check
  • Results
  • Separated concurrent design SW layers
  • DE (high level, CT (low level)
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 13

CPU Ptolemy II (C)

  • Previous approaches
  • Multiple modeling tools (DE, CT), code integration
  • Ptolemy II: Heterogeneous modeling tool
  • Many Models of Computation (MoC)
  • Continous Time, Discrete Event, Synchronous Dataflow, CSP, Finite State Machine, …
  • Focus
  • Tryout single modeling tool approach & multi MoC approach
  • Realization
  • Hierarchical model
  • Whole setup
  • Code generation
  • No formal checks
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 14

CPU Ptolemy II (C)

  • Results
  • Single All-in-one design model, no concurrent design possible
  • Time saving & easy early integration testing
  • Promising approach, but not yet mature enough
  • Extensions & patches to Ptolemy II needed for
  • Code generation: (real-)time support, submodel generation
  • Mechanics (Continuous Time) & Loop Controller modeling (building blocks), …
  • Not all available MoCs can generate code
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 15

Contents

  • Introduction
  • Goals & Challenges
  • Embedded Control Systems Software
  • Design Space Exploration
  • Test Case
  • Demonstration Setup: Production Cell System
  • 6 Embedded Control Systems Software implementations
  • Production Cell ECS Implementations
  • CPU implementations (4)
  • FPGA implementations (2)
  • Evaluation
  • Conclusions & Ongoing work
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 16

FPGA gCSP Handel-C

  • Feasibility study on motion control in FPGA
  • Exploit parallelism
  • Accurate timing
  • Model-based design
  • Choice
  • Modeling tools
  • gCSP + 20-sim (output: floating point control algorithm)
  • Implementation
  • Handel-C
  • No (soft core) CPU
  • Small size Xilinx Spartan III FPGA
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 17

Loop Controller Floating point alternatives

Low precision in small ranges; adaptation of the controllers needed Native data type Integer, CPA 2008 Scheduler / resource manager required High precision; re-use existing controller Soft-core FPU High logic utilization unless stripped High precision; re-use existing controller Soft-core CPU+FPU Only high-end FPGA; expensive High precision; re-use existing controller External FPU High logic utilization Acceptable precision Fixed point library Very high logic utilization High precision; re-use existing controller Floating point library, CPA 2009

Drawback Benefit Alternative

Trade-off between numerical precision and logic cell utilization Trade-off between numerical precision and logic cell utilization

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 18

Results FPGA Usage (integer)

  • Real parallelism
  • 6 Production Cell Units run parallel
  • Integer algorithm (no floating point)
  • Manual translation  time consuming
  • Accurate timing
  • Estimated FPGA Usage
  • Xilinx Spartan 3s1500

89.1% 8.7% 1.6% 0.2% 0.4% Flipflops 71.7% 10.3% 3.6% 0.9% 13.5% LUTs 97.1% 0.6% 2.3% 0.0% 0.0% Memory 32 Used ALUs (26667) (21457) Free (2616) (3089) S&C framework (471) (1090) I/O + PCI (72) (278) Motion profiles (126) (4038) PID controllers (amount) (amount) Element

PID controllers take 50% of the used space, <1% of the code PID controllers run | | @ 1 ms with idle time 99,95%

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 19 Handel-C Floating point library Coregen + Handel-C wrapper Method Language Support Library/ IP-core PCU execution order Implementation platform Accuracy * not yet implemented 32 bit 16 bit / 32-bit* Par Seq Par Seq Par Seq Softcore or hardcore CPU with FPU* Seq Pipelined Seq ANSI-C 32-bit* Floating point FPGA (1) (2) (3) (4) (5) (6) (7) Handel-C Handel-C

FPGA Trade-offs floating point

  • Sequential  Pipelined Handel-C floating point library
  • Sequential  Parallel Production Cell Unit (PCU) execution
  • 32 bit Handel-C  16-bit Xilinx Coregen floating point
  • Soft-core or hard-core CPU with floating point unit.
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 20

Results FPGA Usage (floating point)

  • Less parallelism
  • Sequential PCU execution, but still meeting our deadlines
  • Sequential floating point calculation
  • Central re-used (scheduled) Motion profile + PID controller process
  • Estimated FPGA Usage
  • Xilinx Spartan 3s1500

Floating point library takes 37% of the used space

73.5% 4.2% 1.8% 0.5% 0.3% 19.7% Flipflops 57.6% 5.6% 4.1% 1.1% 4.2% 27.4% LUTs 4 0.0% (5909) (8191) Floating point library + wrappers 97.4% 0.3% 2.3% 0.0% 0.0% Memory 28 Used ALUs (22005) (21457) Free (1250) (1666) S&C framework (534) (1250) I/O + PCI (163) (314) Motion profiles (91) (1251) PID controllers (amount) (amount) Element Red = more resource usage, Green = less resource usage compared to int version

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 21

Evaluation

  • Common CPU & FPGA
  • Hierarchical process-oriented implementations
  • Layered ‘software’ structure with DE + CT/DT parts
  • Create re-usable standardized building blocks
  • Modeling process structures  Implementation efficiency
  • Many small processes  scheduling overhead
  • Often multiple channels between them  Needed: buses
  • Formal verification
  • User-friendly model-to-formal language translation still lacking
  • FPGA implementations
  • Alternative for common CPU / PLC solutions
  • Accurate timing
  • Design time is higher and black box debugging is more difficult
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 22

Evaluation Example Building Block

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 23

Conclusions & Ongoing work

  • Insight maturity (academic) tools for ECS design
  • Standardized process-oriented layered ECS structure
  • Trade-off CPU / FPGA solution
  • CPU: low design time, real-time behaviour  critical issue
  • FPGA: higher design time, more complicated, accurate timing
  • Design Space Exploration results
  • 7 different implementations for same setup
  • Valuable information for improvement design methods & tooling
  • Ongoing work
  • gCSP version 2
  • Design methodology
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 24

Movie

  • Production Cell, CPU controlled: gCSP RTAI version
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 25

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 26

Background Production cell

Extraction belt Rotation unit Extraction unit Feeder unit Moulding unit Feeder belt FPGA I/O board X86 CPU IR block detection

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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 27

Background Design Method ECS SW

Mechatronic system ECS SW Realization

CT SW layers DE SW layers

Integration

Timing (real-) time Implementation Target details Implementation Interfaces DE - CT Interfaces Supervisory & Interaction model Control Law Design Physical System Modeling Top level Abstract SW layer model

  • Approach
  • Stepwise & local refinement
  • From models towards ECS code
  • Verification by simulation & model checking
  • Way of Working
  • Discrete Event
  • Abstract interactions between concurrent

actors

  • Interaction between different MoCs
  • Timing low-level behavior
  • Continuous Time
  • Model & Understand Physical system

dynamics

  • Simplify model, derive the control laws
  • Interfaces & target
  • Add non-ideal components (AD, DA, PC)
  • Scaling/conversion factors
  • Integrate DE & CT into ECS SW
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 28

CPU gCSP QNX (D)

  • Focus:
  • Test QNX real-time operating system
  • QNX
  • Real-time μ-kernel
  • Message passing: channels
  • Transparent distribution
  • Network & local channels are /dev/ nodes
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04-11-2009 HW/SW Design Space Exploration on the Production Cell Setup 29

CPU SystemCSP (G)