High temperature operation of SiC transistors ATW on Thermal - - PowerPoint PPT Presentation

High temperature operation of SiC transistors

ATW on Thermal Management, Los Gatos Cyril BUTTAY1, Marwan ALI2, Oriol AVINO1,2, Hervé MOREL1, Bruno ALLARD1

1 Laboratoire Ampère, Lyon, France 2 Labinal Power Systems, SAFRAN Group, France

23/9/15

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Outline Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

2 / 32

Outline Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

3 / 32

Automotive

Vehicle Location Max Temp (° C) Drive train high temp location 177 Floor 85 Near radiator support structure 100 Back of alternator 160 Cooling circuit 120 Exhaust manifold 649

Most data: Kassakian, J. G. et al. “The Future of Electronics in Automobiles”, ISPSD, 2001, p 15-19

◮ Low-cost, high-volume applications; ◮ Moving to higher voltages (12V->300V for hybrids) ◮ Little cooling headroom with silicon devices (TJ=150 to

175° C)

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Automotive

Vehicle Location Max Temp (° C) Drive train high temp location 177 Floor 85 Near radiator support structure 100 Back of alternator 160 Cooling circuit 120 Exhaust manifold 649

Most data: Kassakian, J. G. et al. “The Future of Electronics in Automobiles”, ISPSD, 2001, p 15-19

◮ Low-cost, high-volume applications; ◮ Moving to higher voltages (12V->300V for hybrids) ◮ Little cooling headroom with silicon devices (TJ=150 to

175° C)

4 / 32

Automotive

Vehicle Location Max Temp (° C) Drive train high temp location 177 Floor 85 Near radiator support structure 100 Back of alternator 160 Cooling circuit 120 Exhaust manifold 649

Most data: Kassakian, J. G. et al. “The Future of Electronics in Automobiles”, ISPSD, 2001, p 15-19

◮ Low-cost, high-volume applications; ◮ Moving to higher voltages (12V->300V for hybrids) ◮ Little cooling headroom with silicon devices (TJ=150 to

175° C) ➟ dedicated cooling circuit for power electronic systems

4 / 32

Aircraft

The trend:

◮ Hydraulic, Pneumatic and Electric

networks co-exist in current systems

◮ More-electric aircraft should reduce

complexity

◮ objective: 1 MW on-board electrical power ◮ From mild to very harsh:

◮ Some system are located in the cabin ◮ Jet engine actuator will face -55°

C to 225° C cycling

◮ Many systems are located in non-pressurised areas

◮ Long system life: around 30 years ◮ Reliability is the main concern

5 / 32

Aircraft

The trend:

◮ Hydraulic, Pneumatic and Electric

networks co-exist in current systems

◮ More-electric aircraft should reduce

complexity

◮ objective: 1 MW on-board electrical power

The environment:

◮ From mild to very harsh:

◮ Some system are located in the cabin ◮ Jet engine actuator will face -55°

C to 225° C cycling

◮ Many systems are located in non-pressurised areas

◮ Long system life: around 30 years ◮ Reliability is the main concern

5 / 32

Aircraft

The trend:

◮ Hydraulic, Pneumatic and Electric

networks co-exist in current systems

◮ More-electric aircraft should reduce

complexity

◮ objective: 1 MW on-board electrical power

The environment:

◮ From mild to very harsh:

◮ Some system are located in the cabin ◮ Jet engine actuator will face -55°

C to 225° C cycling

◮ Many systems are located in non-pressurised areas

◮ Long system life: around 30 years ◮ Reliability is the main concern

5 / 32

Aircraft

The trend:

◮ Hydraulic, Pneumatic and Electric

networks co-exist in current systems

◮ More-electric aircraft should reduce

complexity

◮ objective: 1 MW on-board electrical power

The environment:

◮ From mild to very harsh:

◮ Some system are located in the cabin ◮ Jet engine actuator will face -55°

C to 225° C cycling

◮ Many systems are located in non-pressurised areas

◮ Long system life: around 30 years ◮ Reliability is the main concern

5 / 32

Aircraft

The trend:

◮ Hydraulic, Pneumatic and Electric

networks co-exist in current systems

◮ More-electric aircraft should reduce

complexity

◮ objective: 1 MW on-board electrical power

The environment:

◮ From mild to very harsh:

◮ Some system are located in the cabin ◮ Jet engine actuator will face -55°

C to 225° C cycling

◮ Many systems are located in non-pressurised areas

◮ Long system life: around 30 years ◮ Reliability is the main concern

5 / 32

Space Exploration

◮ NASA missions to Venus and Jupiter

◮ Venus surface temperature : up to 480°

C

◮ Pressure a few kilometres inside Jupiter: 100

bars, at 400° C

◮ Strong thermal cycling, as temperature can drop

to 140K at night;

◮ Other awful conditions: winds, corrosive

• gases. . .

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Deep oil/gas extraction

◮ Continuous operation, relatively low

cycling

◮ Deep drilling: high ambient temperature

(up to 225° C)

◮ Expected lifetime: 5 years ◮ Main requirement: sensors and

datalogging

◮ Example of new applications: downhole

gas compressor

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Maximum operating temperature

0°C 500°C 1000°C 1500°C 2000°C 2500°C 3000°C 10 V 100 V 1 kV 10 kV 100 kV 1 MV Junction temperature Breakdown voltage Silicon 3C−SiC 6H−SiC 4H−SiC 2H−GaN Diamond

Silicon operating temp is intrisically limited at high voltages.

◮ 1200 V devices rated at <200 °

C junction temperature

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Outline Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

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Test configuration

◮ High temperature test system

◮ Silver-sintered interconnects ◮ Ceramic substrate (DBC) ◮ Copper-kapton leadframe

◮ DUT: 490 mΩ SiC JFET from SiCED ◮ characterization:

◮ Tektronix 371A curve tracer ◮ Thermonics T2500-E conditionner 10 / 32

Test configuration

◮ High temperature test system

◮ Silver-sintered interconnects ◮ Ceramic substrate (DBC) ◮ Copper-kapton leadframe

◮ DUT: 490 mΩ SiC JFET from SiCED ◮ characterization:

◮ Tektronix 371A curve tracer ◮ Thermonics T2500-E conditionner 10 / 32

Test configuration

◮ High temperature test system

◮ Silver-sintered interconnects ◮ Ceramic substrate (DBC) ◮ Copper-kapton leadframe

◮ DUT: 490 mΩ SiC JFET from SiCED ◮ characterization:

◮ Tektronix 371A curve tracer ◮ Thermonics T2500-E conditionner

Source: Thermonics T-2500E Datasheet

10 / 32

Static Characterization of 490 mΩ JFET

Buttay et Al. “Thermal Stability of Silicon Carbide Power JFETs” IEEE transactions on Electron Devices, 2013, 60, 4191-4198

2 4 6 8 10 12

Forward voltage [V]

2 4 6 8 10 12

Forward current [A]

• 50 ◦ C
• 10 ◦ C

30 ◦ C 70 ◦ C 110 ◦ C 150 ◦ C 190 ◦ C 230 ◦ C 270 ◦ C 300 ◦ C

VGS = 0 V, i.e. device fully-on

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Power dissipation as a function of the junction temp.

50 50 100 150 200 250 300

Junction temperature [C]

20 40 60 80 100 120 140

Dissipated power [W]

2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

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Thermal Run-away mechanism – Principle

◮ The device characteristic ◮ Its associated cooling system ◮ In region A, the device

dissipates more than the cooling system can extract

◮ In region B, the device

dissipates less than the cooling system can extract

◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

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Thermal Run-away mechanism – Principle

◮ The device characteristic ◮ Its associated cooling system ◮ In region A, the device

dissipates more than the cooling system can extract

◮ In region B, the device

dissipates less than the cooling system can extract

◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

13 / 32

Thermal Run-away mechanism – Principle

◮ The device characteristic ◮ Its associated cooling system ◮ In region A, the device

dissipates more than the cooling system can extract

◮ In region B, the device

dissipates less than the cooling system can extract

◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

13 / 32

Thermal Run-away mechanism – Principle

◮ The device characteristic ◮ Its associated cooling system ◮ In region A, the device

dissipates more than the cooling system can extract

◮ In region B, the device

dissipates less than the cooling system can extract

◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

13 / 32

Thermal Run-away mechanism – Principle

◮ The device characteristic ◮ Its associated cooling system ◮ In region A, the device

dissipates more than the cooling system can extract

◮ In region B, the device

dissipates less than the cooling system can extract

◮ Two equilibrium points: one

stable and one unstable

◮ Above the unstable point,

run-away occurs

13 / 32

Thermal Run-away mechanism – examples

Always stable

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Thermal Run-away mechanism – examples

Always stable Always unstable

14 / 32

Thermal Run-away mechanism – examples

Always stable Always unstable Becomming unstable with ambient temperature rise

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Power dissipation as a function of the junction temp.

50 50 100 150 200 250 300

Junction temperature [C]

20 40 60 80 100 120 140

Dissipated power [W]

2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

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Power dissipation as a function of the junction temp.

50 50 100 150 200 250 300

Junction temperature [C]

20 40 60 80 100 120 140

Dissipated power [W] 1K/W 2K/W 4.5K/W

2.0 A 4.0 A 6.0 A 8.0 A 10.0 A

15 / 32

High Temperature Thermal Management

Buttay et al. “Thermal Stability of Silicon Carbide Power JFETs”, IEEE Trans on Electron Devices, 2014

100 150 200 250 300 350 time [s] 30 40 50 60 70 80 power [W]

current changed from 3.65 to 3.7 A Run-away

SiC JFET:

◮ 490 mΩ, 1200 V ◮ RThJA = 4.5 K/W ◮ 135 °

C ambient

◮ On-state losses

High temperature capability = reduced cooling needs! SiC JFETs must be attached to a low-RTh cooling system.

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Conclusions on high-temp. behaviour of SiC JFETs

◮ SiC JFETs can operate at > 200 °

C

◮ RDSon dependent on temperature

➜ sensitive to thermal run-away

◮ Require efficient thermal management

◮ low thermal resistance (1-2 K/W) ◮ low or high ambient temperature

(> 200 ° C possible)

Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013 2 4 6 8 10 12 Drain-to-Source voltage [V] 10 20 30 40 50 60 70 Drain current [A]

• 50◦C -10◦C 27◦C

70◦C 107◦C 160◦C 196◦C 234◦C 270◦C 49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C 17 / 32

Conclusions on high-temp. behaviour of SiC JFETs

◮ SiC JFETs can operate at > 200 °

C

◮ RDSon dependent on temperature

➜ sensitive to thermal run-away

◮ Require efficient thermal management

◮ low thermal resistance (1-2 K/W) ◮ low or high ambient temperature

(> 200 ° C possible)

Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013 2 4 6 8 10 12 Drain-to-Source voltage [V] 10 20 30 40 50 60 70 Drain current [A]

• 50◦C -10◦C 27◦C

70◦C 107◦C 160◦C 196◦C 234◦C 270◦C 49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C 17 / 32

Conclusions on high-temp. behaviour of SiC JFETs

◮ SiC JFETs can operate at > 200 °

C

◮ RDSon dependent on temperature

➜ sensitive to thermal run-away

◮ Require efficient thermal management

◮ low thermal resistance (1-2 K/W) ◮ low or high ambient temperature

(> 200 ° C possible)

Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013 2 4 6 8 10 12 Drain-to-Source voltage [V] 10 20 30 40 50 60 70 Drain current [A]

• 50◦C -10◦C 27◦C

70◦C 107◦C 160◦C 196◦C 234◦C 270◦C 49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C 17 / 32

Conclusions on high-temp. behaviour of SiC JFETs

◮ SiC JFETs can operate at > 200 °

C

◮ RDSon dependent on temperature

➜ sensitive to thermal run-away

◮ Require efficient thermal management

◮ low thermal resistance (1-2 K/W) ◮ low or high ambient temperature

(> 200 ° C possible)

Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013 2 4 6 8 10 12 Drain-to-Source voltage [V] 10 20 30 40 50 60 70 Drain current [A]

• 50◦C -10◦C 27◦C

70◦C 107◦C 160◦C 196◦C 234◦C 270◦C 49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C 17 / 32

Outline Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

18 / 32

Double Side Cooling

◮ Standard packaging offers cooling through one side of the

die only

◮ “3-D” or “Sandwich” package offers thermal management

• n both sides

◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact

19 / 32

Double Side Cooling

◮ Standard packaging offers cooling through one side of the

die only

◮ “3-D” or “Sandwich” package offers thermal management

• n both sides

◮ Requires suitable topside metal on the die ◮ Requires special features for topside contact

19 / 32

The proposed 3-D Structure

Vbus OUT GND JH JL

◮ Two ceramic substrates, in “sandwich” configuration ◮ Two SiC JFET dies (SiCED) ◮ assembled using silver sintering ◮ 25.4 mm×12.7 mm (1 in×0.5 in)

20 / 32

Ceramic Substrates

SiC JFET Alumina

0.2 mm

0,3 mm

0.16 mm

0,15 mm

Copper

0.15 mm

Gate Source Source Drain

0.3 mm

Scale drawing for 2.4×2.4 mm2 die

◮ Si3N4 identified previously for

high temperature

◮ For development: use of

alumina

◮ Etching accuracy exceeds

standard design rules

◮ Double-step copper etching for

die contact ➜ Custom etching technique

21 / 32

Bonding Material: Silver Sintering

Göbl, C. et al “Low temperature sinter technology Die attachment for automotive power electronic applications” proc of APE, 2006

Silver Paste

◮ Based on micro-scale silver

particles (Heraeus LTS-117O2P2)

◮ Low temperature (240 °

C) sintering

◮ Low pressure (2 MPa) process

No liquid phase involved:

◮ No movement of the die ◮ No bridging across terminals ◮ No height compensation thanks to

wetting

22 / 32

Preparation of the Substrates

plain DBC board

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

plain DBC board 1a - Photosensitive resin coating 1b - Exposure and Development 2 - Etching 3a - resin coating 3b - Exposure and Developpment 4a - Photosentive film laminating 4b - Exposure and Development 5 - Etching 6 - Singulating

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Substrates

◮ Final patterns within 50 µm of desired size ◮ Two designs, for 2.4×2.4 mm2 and 4×4 mm2 dies ◮ Total copper thickness 300 µm, ≈ 150 µm per step

23 / 32

Preparation of the Dies

◮ Standard aluminium topside finish

not compatible with silver sintering

◮ Ti/Ag PVD on contact areas ◮ Need for a masking solution

➜ jig with locating pockets.

Die Mask PVD

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Preparation of the Dies

◮ Standard aluminium topside finish

not compatible with silver sintering

◮ Ti/Ag PVD on contact areas ◮ Need for a masking solution

➜ jig with locating pockets.

Die Mask PVD

Before PVD

24 / 32

Preparation of the Dies

◮ Standard aluminium topside finish

not compatible with silver sintering

◮ Ti/Ag PVD on contact areas ◮ Need for a masking solution

➜ jig with locating pockets.

Die Mask PVD

Before PVD After Ti/Ag PVD

24 / 32

Assembly

Screen printing

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig 8 - Second sintering step

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Assembly

Screen printing 2- Mounting in alignment jig 3- Die-alignment jig, dies and spacer placing 4 - First sintering step 5 - Removal of die- alignment jig 6 - Screen printing on "drain" substrate 7 - Mounting in alignment jig 8 - Second sintering step Result

◮ Ceramic laser-cut jigs for precise alignment of dies and

substrate

◮ Two sintering steps using the same temperature profile

25 / 32

Some results

Size: 25×25 mm2

26 / 32

Some results

26 / 32

Some results

0.9 1.0 1.1 1.2 time [µs] 50 50 100 150 200 Vout [V] 49.9 50.0 50.1 50.2 time [µs]

200°C

◮ 300 Ω Resistive load, 0.5 A current (no cooling system used) ◮ oscillations dues to external layout

26 / 32

Outline Introduction High-Temperature behaviour of SiC Devices Packaging for high-temperature converters Conclusion

27 / 32

Conclusion

◮ SiC JFET able to operate continuously at high temperature(> 200 °

C)

◮ Must be provided with efficient thermal management (RTh =1–2 K/W) ◮ Proposition: introduce dual-side cooling ◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 °

C, including passivation (parylene HT or F)

◮ Proposed etching technique offers satisfying resolution ◮ Silver sintering used for the interconnects, reliability to be investigated

◮ Package for demonstration of technology, no cooling attempted yet!

28 / 32

Conclusion

◮ SiC JFET able to operate continuously at high temperature(> 200 °

C)

◮ Must be provided with efficient thermal management (RTh =1–2 K/W) ◮ Proposition: introduce dual-side cooling ◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 °

C, including passivation (parylene HT or F)

◮ Proposed etching technique offers satisfying resolution ◮ Silver sintering used for the interconnects, reliability to be investigated

◮ Package for demonstration of technology, no cooling attempted yet!

28 / 32

Conclusion

◮ SiC JFET able to operate continuously at high temperature(> 200 °

C)

◮ Must be provided with efficient thermal management (RTh =1–2 K/W) ◮ Proposition: introduce dual-side cooling ◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 °

C, including passivation (parylene HT or F)

◮ Proposed etching technique offers satisfying resolution ◮ Silver sintering used for the interconnects, reliability to be investigated

◮ Package for demonstration of technology, no cooling attempted yet!

28 / 32

Conclusion

◮ SiC JFET able to operate continuously at high temperature(> 200 °

C)

◮ Must be provided with efficient thermal management (RTh =1–2 K/W) ◮ Proposition: introduce dual-side cooling ◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 °

C, including passivation (parylene HT or F)

◮ Proposed etching technique offers satisfying resolution ◮ Silver sintering used for the interconnects, reliability to be investigated

◮ Package for demonstration of technology, no cooling attempted yet!

28 / 32

Conclusion

◮ SiC JFET able to operate continuously at high temperature(> 200 °

C)

◮ Must be provided with efficient thermal management (RTh =1–2 K/W) ◮ Proposition: introduce dual-side cooling ◮ 3D structure using only high-temperature-rated materials

◮ Should be able to operate continuously at 300 °

C, including passivation (parylene HT or F)

◮ Proposed etching technique offers satisfying resolution ◮ Silver sintering used for the interconnects, reliability to be investigated

◮ Package for demonstration of technology, no cooling attempted yet!

28 / 32

This work was funded by Euripides-Catrenes under the grant name “THOR” and FRAE under the grant name “ETHAER”.

cyril.buttay@insa-lyon.fr

29 / 32

Credits

◮ picture of the Airbus A350: airbus ◮ picture of the thrust reverser: Hispano-Suiza

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◮ picture of the Toyota Prius: Picture by Pawel Golsztajn, CC-SA,

available on Wikimedia Commons ❤tt♣✿ ✴✴❝♦♠♠♦♥s✳✇✐❦✐♠❡❞✐❛✳♦r❣✴✇✐❦✐✴❋✐❧❡✿❚♦②♦t❛❴Pr✐✉s✳✷✳❏P●

◮ downhole gas compressor: ❤tt♣✿

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◮ picture of Jupiter: NASA

❤tt♣✿✴✴❡♥✳✇✐❦✐♣❡❞✐❛✳♦r❣✴✇✐❦✐✴❋✐❧❡✿P■❆✵✹✽✻✻❴♠♦❞❡st✳❥♣❣

◮ MOSFET wafers from Mitsubishi

❤tt♣✿✴✴❝♦♠♣♦✉♥❞s❡♠✐❝♦♥❞✉❝t♦r✳♥❡t✴❝✇s✴❛rt✐❝❧❡✴❢❛❜✴ ✸✽✷✸✽✴✶✴s✐❧✐❝♦♥❝❛r❜✐❞❡✇❛❢❡rs

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Static and Dynamic Characterization of 60 mΩ JFET

Falahi et Al. “High temperature, Smart Power Module for aircraft actuators”, HiTEN 2013

2 4 6 8 10 12 Drain-to-Source voltage [V] 10 20 30 40 50 60 70 Drain current [A]

• 50◦C -10◦C 27◦C

70◦C 107◦C 160◦C 196◦C 234◦C 270◦C 49.0 48.8 48.6 48.4 time [µs] 50 50 100 150 200 250 Vout [V] 0.2 0.0 0.2 time [µs]

310°C

Previous results show that SiC JFETs are attractive for > 200 ° C operation:

◮ rated at 1200 V (or more), several Amps ◮ Voltage-controlled devices ◮ No reliability issue related to gate oxide degradation

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Properties of some semiconductors

“Classical” wide-bandgap Si GaAs 3C- SiC 6H- SiC 4H- SiC GaN

Diamond

Bandgap Energy Eg (eV) 1,12 1,4 2,3 2,9 3,2 3,39 5,6

• Elec. mobility

µn (cm2.V−1.s−1) 1450 8500 1000 415 950 2000 4000 Hole mobility µp (cm2.V−1.s−1) 450 400 45 90 115 350 3800 Critical elec. field EC (V.cm−1) 3.105 4.105 2.106 2,5.106 3.106 5.106 107 Saturation velocity vsat (cm.s−1) 107 2.107 2,5.107 2.107 2.107 2.107 3.107 Termal cond. λ (W.cm−1.K−1) 1,3 0,54 5 5 5 1,3 20

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