SLIDE 1 Hardwired Networks on Chip in FPGAs to Unify Functional and Configuration Interconnects
Kees Goossens 1,2 Martijn Bennebroek 3 Jae Young Hur 2 Muhammad Aqeel Wahlah 2 1 Research, NXP Semiconductors 2 Computer Engineering, Delft University of Technology 3 Philips Research
SLIDE 2 2 2008-04-08 NOCS
conventional FPGA – separate hard configuration interconnect and soft NOC proposed FPGA – single hard NOC for configuration, programming, data hardware architecture boot procedure performance : cost analysis conclusions configuration: loading bitstream programming: writing MMIO registers
SLIDE 3 3 2008-04-08 NOCS configuration interconnect
frame
...
CLB frame
... ...
frame CLB frame CLB
... ...
functional IO configuration IO
conventional FPGA
soft IP are configured in configurable logic blocks (CLB) CLBs are interconnected with switch boxes (shown as fat arrows) dedicated configuration interconnect to access frames (minimum unit of reconfiguration) frames and CLBs are orthogonal (22 frames cover 16 CLBs in Virtex4) hence minimum coherent unit of reconfiguration is 22 frames
soft IP
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CFR
unified configuration and functional interconnect
...
...
proposed FPGA
configuration and function region (CFR)
–
– but can be orthogonal and independent as in current FPGAs – interconnected as in current FPGAs (see red arrows): no “tiles”
NOC unifies & connects to
- 1. functional data ports of IP
- 2. functional programming ports of IP (MMIO)
- 3. configuration ports of soft IP (bitstreams)
CFR
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CFR
unified configuration and functional interconnect
...
...
proposed FPGA
configuration and function region (CFR)
–
– but can be orthogonal and independent as in current FPGAs – interconnected as in current FPGAs (see red arrows): no “tiles”
NOC unifies & connects to
- 1. functional data ports of IP
- 2. functional programming ports of IP (MMIO)
- 3. configuration ports of soft IP (bitstreams)
1 & 2 for both soft & hard IP NOC is partially hard & soft enables conversion of data bitstreams
soft IP
functional IO embedded memory, memory controller decryption encryption / CRC
hard IP
soft IP
SLIDE 6 6 2008-04-08 NOCS NI kernel
CFR NI shell
unified configuration and functional interconnect
configuration IO
CFR NI shell NIK NI NIK NIK NIK
...
functional IO embedded memory, memory controller decryption encryption / CRC
NIK
...
NIK B
soft NOC
boot module
NI
proposed FPGA
configuration data functional & programming data
more details on – soft:hard balance – mixing of configuration:functional data
– place of boot module – possibility of bridging to soft NOC shown: – NI kernel to both config & fnal ports – NI kernel to conf ports only – bridge to soft NOC (= NI kernel) – hard NI kernel & shell for shared memory IP (memories) – hard kernel to streaming IPs (en/decryption & IO)
all data types
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NI kernel IP
resp2 req2
port port
NI shell
resp2 req2
port
MMIO slave
req1 resp1
port port
req1 resp1
port master data port
FSM FSM QoS and packetisation FSM
conventional IP & network interface (NI)
IP has data and control (MMIO) ports both are connected to the NOC: unified data & IP programming interconnect
L1 L2 transactions; IP protocol data width peer-to-peer streaming data; NOC link width packets; NOC link width
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paths credits
resp2 req2
port port
req4 resp4 resp4 req4
L1 L2
resp4 req4
port port
resp2 req2
port
MMIO slave
req1 resp1
port port
req1 resp1
port master data port
MMIO slave
port
FSM FSM
NI shell
QoS and packetisation FSM
TDMA table
FSM
conventional NI
programmed using the NOC itself unified IP & NOC programming
NI kernel IP NI shell
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hard NI kernel
CFR (soft IP) paths credits
resp2 req2
port port
soft NI shell
req4 resp4 resp4 req4
L1 L2
resp4 req4
port port
resp2 req2
port
MMIO slave
req1 resp1
port port
req1 resp1
port master data port port
resp3 req3
slave
MMIO slave
port
hard NI shell
TDMA table
NI in FPGA context
NI kernel is hard IP and its shell can be soft or hard hard shell for e.g.: processor, memory, IO soft IP is configured by bitstream transported via the NOC unified interconnect for – data – NI & NOC programming – configuration
FSM FSM QoS and packetisation FSM FSM
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conventional
boot module NOC IP 1: configure module NOC & IP 2: program NOC 3: program IP 4: application functional reset all configuration programming functional
configuration & programming
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conventional new
boot module NOC IP 1: configure module NOC & IP 2: program NOC 3: program IP 4: application functional reset all configuration programming functional boot module 1:
2:
3:
4:
NOC IP 5: application functional reset boot module & NOC functional reset IP
configuration & programming
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NI kernel boot module
TDMA table paths credits
configuration & programming
req2 resp2
port port hard NI shell
connect boot module & (external) memories containing bitstreams to configuration ports of soft IP (CFR)
req1 req resp
port master port
resp1
port port
req3 resp4
port port
L1 L2
req4 resp4
port
programming connection internal history FIFO
d i
address LUT
MMIO slave
QoS and packetisation FSM
bitstream configuration IO
req
port master port
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NI kernel boot module
TDMA table paths credits
configuration & programming
req2 resp2
port port hard NI shell
req resp
port master port
req1 resp1
port port
req3 resp4
port port
L1 L2
req4 resp4
port
programming connection configuration connection internal history FIFO
d i
address LUT
MMIO slave
bitstream configuration IO
QoS and packetisation FSM req
port master port
- 1. program the NOC
- 2. configure the soft IP
send bitstreams over the NOC from (external) memories to CFRs
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NI kernel boot module
TDMA table paths credits
configuration & programming
req2 resp2
port port hard NI shell
- 1. program the NOC
- 2. configure the soft IP
- 3. program the soft IP
“normal boot” of SOC boot module acts as control processor reprogram NOC with connections from boot module to IP MMIO programming ports program IP
req resp
port master port
req1 resp1
port port
req3 resp4
port port
L1 L2
req4 resp4
port
programming connection configuration connection internal history FIFO
d i
address LUT
MMIO slave
QoS and packetisation FSM
bitstream configuration IO
req resp
port master port
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NI kernel boot module
TDMA table paths credits
configuration & programming
req2 resp2
port port hard NI shell
- 1. program the NOC
- 2. configure the soft IP
- 3. program the (soft) IP
- 4. send data to (soft) IP
“functional mode”
req resp
port master port
req1 resp1
port port
req3 resp4
port port
L1 L2
req4 resp4
port
programming connection configuration connection data connection internal history FIFO
d i
address LUT
MMIO slave
QoS and packetisation FSM
bitstream configuration IO
req
port master port
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NI kernel boot module
TDMA table paths credits
configuration & programming
req2 resp2
port port hard NI shell
- 1. program the NOC
- 2. configure the soft IP
- 3. program the (soft) IP
- 4. send data to (soft) IP
- 5. use bitstreams as
functional data (de)compression de/encryption synthesis
etc.
req resp
port master port
req1 resp1
port port
req3 resp4
port port
L1 L2
req4 resp4
port
programming connection configuration connection data connection internal history FIFO
d i
address LUT
MMIO slave
QoS and packetisation FSM
bitstream configuration IO
req resp
port master port
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performance & cost
compare – dedicated configuration interconnect & soft NOC, with – unified hard NOC
– area – functional speed – configuration footprint (bits) – configuration & programming time
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performance & cost
essentially, it all depends on – area soft:hard ≈ 35:1 – speed soft:hard ≈ 3.5:1 – configuration footprint of soft NOC (bitstream) : programming footprint of hard NOC (MMIO registers) ≈ 214:1 resulting in – boot time soft:hard ≈ 1:200 – functional performance:cost (bit/sec:area) soft:hard ≈ 1:147
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performance & cost
percentage cost of router + NI kernel against CFR size (# LUTs) 10% area cost for interconnect implies CFR of ≈ 80,000 LUTs (soft NOC) ≈ 1,400 LUTs (hard NOC)
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performance & cost
# CFRs against their size (# LUTs) # of CFRs of 1000 LUTs ≈ 19 CFRs (soft NOC) ≈ 144 CFRs (hard NOC)
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performance & cost
speed – 118MHz unoptimised soft NOC (90nm) – 500MHz optimised hard NOC (130nm) performance:cost = bit/sec : area – 32 bit x 118 MHz / 8.10 mm^2 = 466 = 1 soft – 32 bit x 500 MHz / 0.23 mm^2 = 69,565 = 147 hard
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performance & cost
configuration speed – 1.9 Gb/s for dedicated configuration interconnect – 8 Gb/s for hard NOC programming speed – 118 MHz soft NOC – 500 MHz hard NOC configuration footprint for soft NOC – 1.8 Mb (8300 LUTs / router+NI) programming footprint for hard NOC – 2100 bit per connection thus – 1 ms per NI for soft NOC – 10.6 microsec per NI for hard NOC
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performance & cost
boot time dedicated configuration + soft NOC – configure soft NOC – configure IP – program soft NOC – program IP – total hard NOC – program soft NOC – configure IP – program IP – total
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conclusions
nice idea but: – low-level implementation of kernel:shell interface would be nice
- investigate impact of mapping shell in LUTs
– performance : cost analysis should be improved (it is in favour of soft interconnects) advantages of real-time NOC not explained “type casting” of bitstreams control data has many cool applications – run-time synthesis & modification of bitstreams
- en/decryption, CRC check, peep-hole / JIT compilation of bitstreams
– run-time relocation of soft IP
- e.g. structural test engines,
re-packing of soft IP on partial dynamic reconfiguration
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