HARDROC2 HARDROC2 HARDROC2 Hardroc2 submission: mid june 08, - - PowerPoint PPT Presentation

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HARDROC2 HARDROC2 HARDROC2 Hardroc2 submission: mid june 08, - - PowerPoint PPT Presentation

Dec 07, 2023 275 likes •480 views

HARDROC2 HARDROC2 HARDROC2 Hardroc2 submission: mid june 08, Hardroc2 submission: mid june 08, Delivered end of october 08: 6 packaged chips, 440 naked dies Package: QFP160 1single row of pads 4.7 mm 28 mm 3mm 4.3 2

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SLIDE 1

HARDROC2 HARDROC2

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SLIDE 2
  • Hardroc2 submission: mid june 08,

HARDROC2

Hardroc2 submission: mid june 08,

  • Delivered end of october 08: 6 packaged chips, 440 naked dies
  • Package: QFP160 1single row of pads

4.7 mm 3mm 28 mm 4.3 2 Plastic (Thin QFP): 1.4 mm (C i 3 4 ) 28 mm (Ceramic: 3.4 mm)

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 2

slide-3
SLIDE 3

HARDROC2: HARDROC1 +modifs

  • Dynam ic range extension

y g – Gain correct.: 8 bits instead of 6: G=0 to 255 (analog G=0 to 2) – 3 shapers, different Rf,Cf and 3 shapers, different Rf,Cf and gains:

  • Fsb1, G= ½,1 / 4 ,1/8,1/16
  • Fsb2, G= 1/8,1 / 1 6 ,1/32,1/64

– 3 thresholds (=> 3 DACs):

  • 10 fC, 100fC, 1pC (megas)
  • 100fC, 1pC, 10pC (GRPC)
  • Correction of the minor bugs of

HR1: MASK, memory pointer (dummy frame)

  • 8 7 2 SC registers, default config
  • Pow er pulsing:

p g – Bandgap (redesigned)+ ref Voltages + master I: power pulsed – POD module (power budget)

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 3

POD module (power budget)

slide-4
SLIDE 4

SC/Read pb

Di it l SW

  • To spare output PADS and to avoid parasitics on the

Slow control Data input

sr rstb rstb_read Digital SW

To spare output PADS and to avoid parasitics on the SC registers, SELEC + switch to deliver: – sr_sc, clk_sc, rstb_sc – sr_read, clk_read, rstb_read

Probe Select input

_ rstb_sc selec

– Pb=digital sw and reset active low => reset of the SC registers when SELEC switched on the read register

  • Read register not essential but usefull for debug and

characterisation => Focused Ion Beam on 2 packaged chips to be able to use the Read register

  • SC loading:

– 872 SC parameters – Vddd=4V necessary to load some SC config y g

strap

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 4

slide-5
SLIDE 5

3 10bit-DACs

  • DAC0 : fine= > -1 .1 m V/ UDAC

/

– Vmax Vmin std – 2.3268 1.9966 0.09

  • DAC0 : coarse = > -2 .2 1 m V/ UDAC

DAC0 : coarse > 2 .2 1 m V/ UDAC

– Vmax Vmin std – 2.3271 1.66379 0.192

  • DAC1 : coarse = > -2 .0 6 m V/ UDAC

DAC1 : coarse > 2 .0 6 m V/ UDAC

  • DAC2 : coarse = > -2 .1 2 m V/ UDAC

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 5

slide-6
SLIDE 6

FSB measurements

<>dc fsb: Independant of G <>=2.14V = pedestal equiv. to DAC0 (coarse) ≈90 G=256 Pedestal= 90 ±2 G=256 G=0

All i ON 70 V 750 V S/N 93

FSB0 , 1 0 0 fC injection, G= 1 2 8 : optim um Signal/ Noise ratio

All swi ON 70mV, tp=23ns σ=750µV S/N=93 Sw_150fF on 203 mV 1.2mV 168 Sw_100fF on 243 mV 1.3 mV 187 Sw_100k and sw_100fF on 153 mV 930 µV 165 Sw_50fF on 100 mV 1.5 mV 67 No swi on (=> internal 20fF, 100k l ) 421 mV 1.8 mV 233

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 6

100k only)

slide-7
SLIDE 7

Waveforms and Xtk: scope measurements

FSB0, Qinj=100fC Xtk x10 FSB1 (0100), Qinj=1 pC FSB2 (0100), Qinj=10 pC FSB0 normalised to 1 Analog Xtk < 1%

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 7

Testboard wo any decoupling cap.

slide-8
SLIDE 8

Digital Xtk (board wo DECOUPLING CAP)

li f h di i h f h di

  • Coupling of the discri output to the FSB output of the direct

neighbors

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 8

slide-9
SLIDE 9

Digital Xtk measurements (board wo DECOUPLING CAP)

ch39

( f f f k d

ch39 ch41

  • FSB0 ( sw _ Cf= 1 0 0 fF, sw _ Rf= 1 0 0 k and

G= 1 4 4 ) :

  • 1 0 0 fC in ch4 0 , Vth0 = 2 0 5 = > 2 0 0 m V,

trigger for Vth0 < 2 0 5

ch38

trigger for Vth0 < 2 0 5

  • Qinj= 1 pC ( 1 V@2 0 dB in 1 0 pF) , no trigger on

direct neighbours

  • Qinj> 2 .5 pC ( fsb0 sature) , trigger on ch3 9 and

ch4 1 ie 4 %

ch40

ch4 1 ie 4 %

  • Qinj> 7 pC ( fsb0 sature) , trigger on ch3 8 ,3 9

and 4 1 ,4 2

  • Qinj> 5 6 pC, triggers on 3 7 ,3 8 ,3 9 and 4 1 ,4 2
  • 1 0 0 pC, triggers on ch 3 4 ,3 5 ,3 6 ,3 7 ,3 8 ,3 9 and
  • FSB1 ( 5 0 f,1 0 0 fF,1 0 0 k,5 0 k and G= 1 4 4 and Gnm os= 1 0 0 0 ) :

1 0 0 pC, triggers on ch 3 4 ,3 5 ,3 6 ,3 7 ,3 8 ,3 9 and ch 4 1 ,4 2 ,4 3 ,4 4 ,4 5 ,4 6

  • FSB1 ( 5 0 f,1 0 0 fF,1 0 0 k,5 0 k and G= 1 4 4 and Gnm os= 1 0 0 0 ) :
  • 1 pC, Vth1 = 4 4 3 = > 7 3 0 m V, trigger for Vth1 < 4 4 5
  • Qinj= 1 pC ( 1 V@2 0 dB in 1 0 pF) , no trigger on direct neighbors
  • Qinj> 5 6 p, trigger on ch3 9 and 4 1
  • 1 0 0 pC, triggers on ch3 9 and ch 4 1
  • FSB2 ( 5 0 f,1 0 0 fF,1 0 0 k,5 0 k and G= 1 4 4 and Gnm os= 0 0 1 0 ) :
  • 1 0 pC, Vth2 = 2 3 0 = > 7 3 0 m V, trigger for Vth2 < 2 3 3

Qi j 1 C ( 1 V@2 0 dB i 1 0 F) t i di t i hb

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 9

  • Qinj= 1 pC ( 1 V@2 0 dB in 1 0 pF) , no trigger on direct neighbors
  • Qinj= 1 0 0 pC, no triggers on neighbours
slide-10
SLIDE 10

8bit PMOS MIRRORS: linearity measurement

Vout

  • Allows accomodating the gain according to the

detector choice

Vout Qinj=100fC

  • PMOS gain: 8 bits/channel
  • Binary Gb= 0 to 255
  • Analog G = 0 to 2

g

  • Current mirrors mismatch between channels

(small size transistors to optimise the speed):

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 10

( p p ) layout redone in HR2 to improve the uniformity

slide-11
SLIDE 11

FSB0 scurves: HR1 /HR2 before and after gain correction

HR1 before cor. HR2 before cor. HR2 before cor.

Qinj=100fC Qinj 100fC

HR1 after cor. HR2 after cor.

Pedestal substracted 9% 5% 6.7% 1.4%

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 11

slide-12
SLIDE 12

SCURVES: FSB0,1,2

  • Gain=144 for all channels before correction

In GREEN= after gain correction

Gain 144 for all channels before correction

  • Gain correction performed for each channel on FSB0, not efficient on FSB1

and FSB2 as non uniformity is dominated by non uniformity of NMOS mirrors used to change Gnmos

g 6 7% 1 3%

FSB2 , 1pC FSB0 , 100 fC

6.7% 1.3% 7% 6% 5 5%

FSB2 10pC FSB1 , 1pC

5.5% 5% 3%

FSB2 , 10pC

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 12

slide-13
SLIDE 13

POWER CONSUMPTION

  • Maximum power available:

PA

5.46mA

DAC

0.84mA

3 FSB

12.3mA

BG

1.2mA

SS

9 3mA

ddd

0 67mA

  • Maximum power available:

– 10 µW/ch with 0.5% duty cycle – => 640µW/3.5V=180 µA for the entire chip

SS

9.3mA

vddd

0.67mA

3 Discris

7.3mA

vddd2

0.4mA

(=0 if 40MHz OFF)

entire chip – OFF= Ibias _cell switched off during interbunch – SW added in HR2 to switch off

OFF)

TOTAL

38mA all the master Ibias, Vref, V_BG…

Pwr_on_a alone (FSB0 and discri0 ON only) 14.9mA Pwr_on_dac 1.025mA Pwr_on_d 0.93mA ALL ON 17 mA ALL OFF < 4 µA

  • Without SS:

– 38-9=29mAx3.3V≈100mW – 1.5mW/ch 7 5 µW/ch with 0 5% duty cycle

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 13

– 7.5 µW/ch with 0.5% duty cycle

slide-14
SLIDE 14

Power pulsing of HR2: « Awake » time

PWR ON PWR ON PWR ON FSB0 25 µs 8 µs

  • PWR ON: ILC like (1ms,199ms)
  • All decoupling capacitors removed
  • PP of the analog part:

Trigger

– Input signal synchronised on PWR ON – => Awake time= 8 µs

  • Power pulsing of the DAC:

– 25 µs (slew rate limited)

DAC output (Vth)

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 14

slide-15
SLIDE 15

Power On Digital module (POD)

  • PowerON start/stop clocks and

StartLVDS POD module

  • PowerON start/stop clocks and

LVDS receiver bias current to meet power budget.

LVDS Receiver Enable Clock f A i i i d ClkOut Clkin

  • LVDS receivers for

RazChn/NoTrig and ValEvt ON during PowerOnAnalog (during

for Acquisition and Conversion PowerOnDigital StartReadOut StartReadOutInt Clkin Enable Clock for Readout Rstb Enable EnableClock

du g

  • e O

a og (du g bunch crossing)

Acquisition Conversion Readout (99% time) Phases

  • Clock is started

h l bl d d

EndReadOut ClkOut Enable PowerOnInt Chip 1 PowerOnInt Chip 2

asynchronously, enabled and stopped synchronously (at ‘0’)

  • 2 operation modes :

PowerOnInt Chip N

p

– Acquisition, Conversion common to all managed by DAQ DAQ – Readout daisy chained managed by StartReadOut and EndReadOut

  • POD successfully tested on

testbench

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 15

EndReadOut

slide-16
SLIDE 16

CONCLUSION

  • HR1 bugs corrected (Mask memory pointer)
  • HR1 bugs corrected (Mask, memory pointer)
  • 0.5% duty cycle pwr pulsing: pwr <8µW per channel
  • Better uniformity between channels before correction: 7%,

y , down to 1.5% (fsb0) after correction (that might be not necessary for RPC)

  • Scurves@ 1pC and 10 pC OK dispersion=5%
  • Scurves@ 1pC and 10 pC OK, dispersion=5%
  • HR2: operates in full I LC m ode and is suitable for m2 ( No

p ( analog output) and production when validated on detectors. 400 HR2 i I2A k i (USA) t b

  • 400 HR2 are in I2A packaging company (USA) to be

packaged in plastic TQFP160.

  • Must be TESTED (=characterisation=>30minutes/chip)

( p)

  • Power pulsing tested on testbench. To be tested in test beam

h il bl h / / i f

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 16

  • Datasheet available on http:/ / om ega.in2 p3 .fr
slide-17
SLIDE 17

ANNEX

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 17

slide-18
SLIDE 18

HARDROC2: analog part

Slow Channel

Q Read hold

HARDROC1

½,1/4,1/8,1/16

PA

Q_Read hold Multiplex Out_ss

FSB0 Discri 0

Out fsb

LATCH 0

trig_0

Q_Read

razchn l t

8 bits correct.

Vth0: 10fC to 100fC Out_fsb

NOR64_0

Q_Read

trigger0

Qmask0

valevt

872 SC parameters (default config) Gain FSB1

½,1/4,1/8,1/16

Discri 1

NOR64_1 trig_1

LATCH 1

trigger1 razchn valevt

(default config)

½,1/4,1/8,1/16 (Default: G=0100)

Discri 2

Vth1: 100fC to 1pC

Encoder LATCH 2

trigger0 trigger1 trigger2 encod0 encod1

Qmask1

Gain FSB2

1/8,1/16,1/32,1/64 (D f lt G 0100)

Discri 2

NOR64_2 trig_2

Q_Read

trigger2

Qmask2

razchn valevt

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 18 (Default: G=0100)

Vth2: 1pC to10pC

Qmask2

slide-19
SLIDE 19

HR2 in TQFP160

pa 3> 2> 1> 0> > > > > > > > > > > pa ss ss capa nmos fsb0 fsb1 fsb _fsb _ss a sb fsb aq q fsb d d 1 2 3 4 120 119 118 160 159 158 157 156 155 154 153 152 151 151 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 vssi vdd_pad in<14> in<15> vddd sr_load sr_out i gnd_p in<13 in<12 in<11 in<10 in<9> in<8> in<7> in<6> in<5> in<4> in<3> in<2> in<1> in<0> gnd_p vssa vdd_s gnd_s gnd_c gnd_n gnd_f gnd_f vdd_f vref_ vref_ ibi_pa ib_w ibi_fs ibo_f ib_ota

  • ut_q
  • ut_f

vssa vssm gnd_d ibi_d ibo_d gndd vssd 4 5 6 7 8 9 10 11 12 117 116 115 114 113 112 111 110 in<15> in<16> in<17> in<18> in<19> in<20> in<21> in<22> in<23> sr_in sr_ck sr_rstb select end_readout2 end_readout1 start_readout2 start_readout1 t t b 12 13 14 15 16 17 18 19 20 109 108 107 106 105 104 103 102 101 in<23> in<24> in<25> in<26> in<27> in<28> in<29> in<30> in<31> rst_counterb ChipSatb TransmitOn2b TransmitOn1b Dout2b Dout1b rtn resetb d 20 21 22 23 24 25 26 27 28 101 100 99 98 97 96 95 94 93 in<31> gnd_pa in<32> in<33> in<34> in<35> in<36> in<37> in<38> vssd ck_40n ck_40p ck_5n ck_5p raz_chnn raz_chnp val_evtn l t 28 29 30 31 32 33 34 35 36 93 92 91 90 89 88 87 86 85 in<38> in<39> in<40> in<41> in<42> in<43> in<44> in<45> in<46> val_evtp start_acq ib_rec pwr_on_d pwr_on_a pwr_on_adc pwr_on_dac trig_ext t t i 0 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 85 84 83 82 81 in<46> in<47> in<48> in<49> vdd_pad

  • ut_trig0
  • ut_trig1
  • ut_trig2

vddd vddd

HR2 status,CALICE meeting,DAEGU, KOREA, 18 Feb 09, NSM 19

vssi gnd_pa in<50> in<51> in<52> in<53> in<54> in<55> in<56> in<57> in<58> in<59> in<60> in<61> in<62> in<63> gnd_pa vssa ctest vdd_pa vgain_pa vcasc_pmos holdb gnd_nmos vcasc_nmos gnd_dac vdd_dac vdd_bg gnd_bg v_bg ibi_otadac iref_dac ibi_otabg vssa vssm vdd_d vth2 vth1 vth0 vddd2