HARDROC 3 for SDHCAL 02 / 02 / 2014 - HGC4ILD Workshop OMEGA - - PowerPoint PPT Presentation

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HARDROC 3 for SDHCAL 02 / 02 / 2014 - HGC4ILD Workshop OMEGA - - PowerPoint PPT Presentation

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HARDROC 3 for SDHCAL 02 / 02 / 2014 - HGC4ILD Workshop OMEGA microelectronics group Ecole Polytechnique CNRS/IN2P3 , Palaiseau (France) Organization for Micro-Electronics desiGn and Applications ROC chips for ILC prototypes SPIROC2 ROC

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SLIDE 1

Organization for Micro-Electronics desiGn and Applications

HARDROC 3 for SDHCAL

OMEGA microelectronics group

Ecole Polytechnique CNRS/IN2P3 , Palaiseau (France)

02 / 02 / 2014 - HGC4ILD Workshop

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SLIDE 2

2

ROC chips for ILC prototypes

 ROC chips for technological prototypes: to study the feasibility of large scale, industrializable modules (Eudet/Aida funded)  Requirements for electronics

  • Large dynamic range (15 bits)
  • Auto-trigger on ½ MIP
  • On chip zero suppress
  • 108 channels
  • Front-end embedded in detector
  • Ultra-low power : 25µW/ch

SPIROC2

Analog HCAL (AHCAL)

(SiPM) 36 ch. 32mm²

June 07, June 08, March 10, Sept 11 HARDROC2 and MICROROC

Semi Digital HCAL (sDHCAL)

(RPC, µmegas or GEMs) 64 ch. 16mm²

Sept 06, June 08, March 10 SKIROC2

ECAL

(Si PIN diode) 64 ch. 70mm²

March 10

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SLIDE 3

From 2nd generation…

3

Acquisition 1ms (.5%)

A/D conv.

.5ms (.25%)

DAQ

.5ms (.25%)

1% duty cycle IDLE MODE 99% idle cycle

198ms (99%)

time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 µs)

Acquisition 1ms (.5%)

A/D conv.

.5ms (.25%)

DAQ

.5ms (.25%)

1% duty cycle IDLE MODE 99% idle cycle

198ms (99%)

time Time between two trains: 200ms (5 Hz) Time between two bunch crossing: 337 ns Train length 2820 bunch X (950 µs)

Acquisition

A/D conv. DAQ IDLE MODE Chip 0 Chip 1

Acquisition

DAQ IDLE MODE IDLE Chip 2

Acquisition

IDLE MODE IDLE Chip 3

Acquisition

IDLE MODE IDLE Chip 4

Acquisition

IDLE MODE IDLE DAQ A/D conv. A/D conv. A/D conv. A/D conv.

Acquisition

A/D conv. DAQ IDLE MODE Chip 0 Chip 1

Acquisition

DAQ IDLE MODE IDLE Chip 2

Acquisition

IDLE MODE IDLE Chip 3

Acquisition

IDLE MODE IDLE Chip 4

Acquisition

IDLE MODE IDLE DAQ A/D conv. A/D conv. A/D conv. A/D conv.

Chip 0 Chip 1 Chip 2 Chip 3 Chip 4 5 events 3 events 0 event 1 event 0 event

Data bus

 2nd generation chips for ILD

 Auto-trigger, analog storage and/or digitization  Token-ring readout (one data line activated by each chip sequentially)  Common DAQ  Power pulsing : <1 % duty cycle

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SLIDE 4

 3rd generation chips for ILD

 Independent channels (zero suppress)  I2C link (@IPNL) for Slow Control parameters and triple voting

  • configuration broadcasting
  • geographical addressing

 HARDROC3: 1st of the 3rd generation chip to be submitted

– Received in June 2013 (SiGe 0.35µm) (AIDA funded) – Die size ~30 mm2 (6.3 x 4.7 mm2) - Packaged in a QFP208

…To 3rd generation

4

RPC cross section

1m2 RPC [IPNL]

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SLIDE 5

HR3: Simplified schematics

5

Variable Gain PA

Gain correction

8 b its/ch an n el

Bipo lar FAST Shaper 0

Vth 0 Vth1

Latch RS Latch RS

SLO W Shaper Chj

Chj_trig0 Chj_trig1

+

H old

Read

M ultiple x Charge output

Discri. Discri

D 0 D 1

Bipo lar FAST Shaper 1 Bipo lar FAST Shaper 2

D 2 Vth2 m ask0 m ask1

Latch RS

m ask2

Read

Chj_trig2 nor6 4 _0 _<j>

Read

nor6 4 _1 _<j>

Read

nor6 4 _2 _<j>

Vth0: 10fC to 100fC Vth1: 100fC to 1pC Vth2: 1pC to10pC trigger0<j> trigger1<j> trigger2<j> ENCOD ER trigger0 trigger1 trigger2

e ncod0 <j> e ncod1 <i>

Ctest ch<j> Slow Ctrl

2 pF

Ctest_Chj

trigger0<j> valid _trig0 W R_M EM <j>

R AM 8 e ve nts x (1 2 + 2 ) bits 1 2 B it counte r B CID

1 Digital M em ory/ch

trigger1<j> valid _trig1 trigger2<j> valid _trig2 trigr0<j> trigr1<j> trigr2<j>

64 channels

D AC1 1 0 bits Vth1 D AC0 1 0 bits Vth0

O R64 DIGITA L PA RT Common to the 64 channels

nor6 4 _0 <0 :6 3 > nor6 4 _2 <0 :6 3 > nor6 4 _1 <0 :6 3 > D AC2 1 0 bits Vth2

 64 channels with current preamplifiers  Trigger less mode (auto trigger 15fC up to 10pC)  Gain correction (max factor 2)  3 shapers + 3 discriminators (encoded in 2 bits for readout)  I2C link for Slow Control  Independent channels with zero suppress  Max 8 events / channel with 12-b time stamping  Integrated clock generator: PLL  Power pulsing mode

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SLIDE 6

Analog Part: FSB Linearity

FSB0 FSB0: 5s noise limit= 15 fC FSB1 FSB2 Up to 10 pC Up to 50 pC

6

Fast shaper outputs (mV) vs Qinj (fC) 50% trigger efficiency (DAC units) vs Qinj (fC) Dynamic range: 15fC - 50 pC

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SLIDE 7

Gain correction / Scurves

7

HR3: extracted 50% Scurves point vs Channel number

Before: ± 17 DACU After: ± 8 DACU (± 6 fC)

50% point

± 25fC

Qinj=100fC

50% point

± 5fC

HR2 gain correction

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SLIDE 8

8

New Slow Control: I2C

  • I2C standard protocol access (max 127 chip / line)
  • Possibility to broadcast a default configuration to all the chips
  • Read and write access to a specific chip with its geographical address
  • Triple voting for each parameter (redundancy)
  • Read back of control bit (even if the chip is running / copy)

Write frame: Read frame:

S A A A P Slave address Reg address data W S R A A P Slave address data S A A P Slave address Reg address W

Clock Data

Master

Slave 1 Slave 2 Slave 3 Slave x

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SLIDE 9

9

  • I2C Write acces : Chip number (ID): 0xE2 / Reg @: 0x73 / WrData: 0x83

I2C measurements

  • I2C Read acces : Chip number (ID): 0xE2 / Reg @: 0x73
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SLIDE 10

1

PLL measurements

5MHz  40 MHz  2 clocks are needed to start the chip

 Slow Clock (1-10 MHz) related to the beam train (for Time stamping and data readout)  Fast clock (40-50MHz) for internal the state machines

 A PLL (clock multiplier) has been designed to generate the fast clock

 Multiplication factor is (N+1) / N is a SC parameter (1 to 31)  Full chain tested using PLL

45 46 47 48 49 50 10 20 30 40

Duty Cycle in % Output frequency in MHz

Duty Cycle in % vs OutFreq in MHz Freq input fixed @ 5MHz

Tlock = 260 µs PowerOnD Out_PLL

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SLIDE 11

Zero suppress: Memory mapping

7 15 576 0 7-bit C hipID 0 0 0 0 0 P

R E A D (re a d o u t)

C hn # (6 bit) P # e vt 4b G e ne ra l da ta : m a x 64 w ords P P B C ID + C ha rge

  • f C H 0 : m a x 8 w ords

1 1 P P 1 B C ID c hn 0 : 12 bits E 1 E 0 B C ID c hn 1 : 12 bits B C ID c hn 1 : 12 bits B C ID + C ha rge

  • f C H 1 : m a x 8 w ords

P P B C ID + C ha rge

  • f C H 62 : m a x 8 w ords

P P B C ID c hn 62 : 12 bits B C ID c hn 62 : 12 bits B C ID c hn 63 : 12 bits B C ID c hn 63 : 12 bits B C ID + C ha rge

  • f C H 63 : m a x 8 w ords

B C ID c hn 0 : 12 bits E 1 E 0 E 1 E 0 E 1 E 0 E 1 E 0 E 1 E 0 E 1 E 0 E 1 E 0 C hn # (6 bit) P # e vt 4b 1

  • Chip ID is the first to be outputted during

readout (MSB first)

  • MSB of each word indicates type of data:

– “1”: general data (Hit ch number and number of events) – “0”: BCID + encoded data

  • A parity bit/word
  • Up to 9232 bits (577x16) during readout
  • Example of number of bits during

readout:

HR2 HR3

1 chn hit 160 48 8 chn hit 1280 272 4 chn hit @ same time 160 144 10 chn hit @ same time 160 336

11

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SLIDE 12

Zero suppress: Tests

  • Zero suppress (only hit channels are readout): test OK
  • Roll mode SC : test OK

– If RollMode = “0”  Backward compatibility with 2Gen ROC chips behavior

  • Only the N first events are stored

– If RollMode = “1”  3Gen ROC chips behaviour

  • Use the circular memory mode
  • Only the N last events are stored
  • “Noisy Evt” SC: 64 triggers => Noisy event => no data stored : test OK
  • “ARCID” SC (Always Read Chip ID): test OK

– If ARCID = 0  Backward compatibility: No event  No readout – If ARCID= 1  New behavior: No event  Read CHIP ID

Signal injected ch 20 and ch 43

12

slide-13
SLIDE 13

1 3

Power pulsing in HR chips

Power supply

HR3 with LVDS

(5M + 40M) µW / channel

HR2 with LVDS

(5M + 40M) µW / channel

PowerOnA (Analog) 1650 1325 Only PowerOnDAC 55 50 Only PowerOn D 725 50 Power-On-All 2430 1425

Power-On-All @ 0,5% duty cycle 12,2 7,5

  • Compared to HR2, HR3 power consumption is higher due

to:

– The extended dynamic range (from 15pC to 50pC) – The integration of the zero suppress algorithm

  • If the PLL is used, the power consumption is increased by

3% (due to the PLL VCO)

DAC output (Vth) Trigger 25 µs PWR ON HR2

 Power pulsing:

 Bandgap + ref Voltages + master I: switched ON/OFF  Shut down bias currents with vdd always ON

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SLIDE 14

1 4

Power pulsing: Testbeam HR2

– SDHCAL technological proto with up to 50 layers (7200 HR2 chips) built in 2010-2011. – Scalable readout scheme successfully tested – Complete system in TB with 460 000 channels, AUTOTRIGGER mode and power pulsing (5%)

1 m3 RPC detector, 40 layers 370 000 channels

@IPNL Lyon

Vth0 Vth1 Vth2

1m2 RPC [IPNL] – 144 ASICS

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SLIDE 15
  • Good analog performances
  • Dynamic range extended up to 50 pC
  • Circuit is able to work with only 1 external clock (thanks to PLL)
  • New I2C tested successfully
  • New digital features validated on testboard
  • Zero suppress, roll mode, ARCID mode and Noisy event mode
  • External trigger available to be able to check the status of each channel
  • Next steps
  • Production run (HR3 + 11 others chips) will be submitted mid-February 2015
  • 2-3m long RPC chambers to be built and equipped with HR3 in 2015
  • Moving SPIROC / SKIROC to 3rd generation
  • Much more complicated due to internal ADC / TDC / SCA management
  • Integration and tests of HR3 on the 2-3m long RPC will be very helpful

Summary and next steps

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