GHDL and the economy of EDA FOSS Tristan Gingold - FSiC 2019 1 / - - PowerPoint PPT Presentation

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GHDL and the economy of EDA FOSS Tristan Gingold - FSiC 2019 1 / - - PowerPoint PPT Presentation

Jan 22, 2024 819 likes •1.06k views

GHDL and the economy of EDA FOSS Tristan Gingold - FSiC 2019 1 / 21 What is GHDL ? A Free (GPL v2+) VHDL simulator Supports IEEE 1076 (VHDL) 1987, 1993 and 2008 (partially) Compiled Command line tool Binaries for Linux (x86,

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GHDL and the economy of EDA FOSS

Tristan Gingold - FSiC 2019

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What is GHDL ?

  • A Free (GPL v2+) VHDL simulator
  • Supports IEEE 1076 (VHDL) 1987, 1993 and 2008

(partially)

  • Compiled
  • Command line tool
  • Binaries for Linux (x86, x64), Windows, MacOS
  • Generates VCD, GHW and FST waveforms
  • VPI support (for external tools like cocotb)
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What does it support ?

  • Full support of VHDL-87 and 93

– Your design should work

  • Partial support of VHDL-2008

– Good enough for VUnit, OSVVM and UVVM.

  • Support inline PSL (assert and cover)

– Creates an NFA

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Internal view

Scanner Parser Semantic analysis Transformation Library manager Code generation llvm, gcc, mcode

  • Generate tokens
  • Generate the AST
  • Create links in the AST
  • Semantic checks
  • Rewrite as processes
  • Generate a low-level AST
  • Generate object code

scan.adb parse.adb sem*.adb canon.adb trans*.adb AST mcode

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Elaboration

  • Object code can be generated:

– File per fjle (gcc or llvm backend)

  • No C generated, it is ghdl1

– For the whole design (mcode – an internal JIT)

  • Very fast and lightweight, no opt
  • Elaboration is dynamic

– Done early during execution – Prevents many optimizations

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Abstract Syntax Tree - AST

  • Represent the sources
  • Closely follow the VHDL Language Reference Manual

– Simplify the support of the language – Possible as the LRM is well/correctly written

  • Strongly typed

– Each fjeld of a node has a type

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Abstract Syntax Tree - AST

  • Nodes are represented by 32-bit numbers

– Shorter than pointers on 64 bit platforms

  • Nodes size is fjxed (32 or 64 bytes)

– Possible to implement parallel tables – To extend the nodes (eg: in translate)

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Abstract Syntax Tree - AST

  • Meta-description

– Type: node, list, number, fmags, … – Links: own, reference, maybe-own – Simplify package instantiation or dump.

  • Described using ad-hoc comments
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Why Ada ?

  • GHDL is written in Ada
  • A subset (imperative, sequential)
  • Strong typing
  • Modular language
  • Stable
  • VHDL is very similar to Ada

– If you know one, you will be familiar with the other

  • Makes contribution less easy ?
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The future of GHDL

More vhdl-2008 features GUI – easier to use Speed/performances Verilog/SV support Language server protocol Synthesis (netlist generation) More PSL More VPI Coverage AMS SystemC Checkpoints *Spice interface

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Collaboration: analog

  • VHDL-AMS:

– Parsing and analysing AMS extensions – DAE solver

  • Spice/GnuCap

– Linking simulation kernel together

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Collaboration: Synthesis

  • Proof of concept (ghdlsynth)

– Need to support arrays – Yosys module

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Collaboration: SystemVerilog

  • Mixed vhdl + verilog/systemverilog

– Even support SystemC ?

  • SystemVerilog

– Start from scratch ? – Or start from an existing simulator ?

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Priority ?

More vhdl-2008 features GUI – easier to use Speed/performances Verilog/SV support Language server protocol Synthesis (netlist generation) More PSL More VPI Coverage AMS SystemC Checkpoints *Spice interface

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The economy of EDA FOSS

  • My experience
  • My feelings
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Why writing FOSS EDA tool ?

  • By philosophy

– I want FOSS everywhere

  • Academic research project

– I need a tool for my research project or my PhD

  • To understand a technology

– I’d like to learn a language

  • To improve my tooling

– The tool is crappy – I need a specifjc feature

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Audience / market

  • Maybe 100x CS engineers than EE engineers

– Do not expect a lot of users!

  • Cost: you just need a computer to write an app,

you need >40$ for a little EE project

  • Culture: FOSS is SW fjrst

– Many HW designers are happy with closed

source EDA

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Contributions

  • Skill: EE is not CS

– HW people aren’t SW developers – SW people aren’t interested in HW design

  • Tools are already available

– Free HDL simulators, synthesis, P&R – Why working on a FOSS project ?

  • Do not expect many contributions

– YMMV ?

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Complexity

  • Lot’s of complex algorithms or data structure

– BDD, SAT, NP-hard, simulated annealing…

  • Makes EDA very interesting / challenging
  • But not for beginners
  • Need more time to tune an algorithm
  • Reuse existing libraries

– When possible – When existing

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Closed ecosystem

  • Most low-level information are not available

– FPGA bitstream and characteristics – Foundry processes – IP cores are encrypted – File formats (schematic, waveforms…)

  • Diffjcult to write a FOSS element
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Maturity

  • Prototype vs mature software
  • Users need reliable and stable software
  • Authors usually need a prototype
  • Technology changes quickly
  • Need to use industry fjle formats
  • My experience:

– every VHDL feature has been used – diffjcult to support only a subset