Gates - Part 1 September 11, 2008 Typeset by Foil T EX Gates are - - PowerPoint PPT Presentation

Gates - Part 1

September 11, 2008

– Typeset by FoilT EX –

Gates are built with Transistors

Gate Drain Source

nFet

Drain Source 3 volts Current Flows

nFet On

Drain Source 0 volts Current No Flows

nFet Off N-type field-effect transistor = nFet

– Typeset by FoilT EX – 1

Gates are built with Transistors

Gate Drain Source

pFet

Drain Source Current Flows 0 volts

pFet On

Drain Source Current No Flows 3 volts

pFet Off P-type field-effect transistor = pFet

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Complement

Also known as invert or not. X F 1 1

X X’

This is a schematic symbol. It is a graphical representation of a circuit which implements the

• perations.

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FET-Based Inverter

Vcc = 3V

Vout Vin

GND = 0V Vcc = 3V

3V 0V ON OFF

GND = 0V Vcc = 3V

OFF ON 3V 0V

GND = 0V

– Typeset by FoilT EX – 4

AND and OR Gates

And Gate

A B Y=A * B

A B Y = A • B 1 1 1 1 1

Or Gate

A B Y = A + B

A B Y = A + B 1 1 1 1 1 1 1

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Boolean Expressions and Gates

Each boolean expression has a corresponding realization with logic gates. F = A’ + BC

A B C F

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NAND Gates

NAND A B F=(A•B)’ 1 1 1 1 1 1 1

A B Y = not(A * B)

A B Y=not(A*B)

AND

A B Y=A * B

Y is true iff A AND B are true NAND

A B Y=not(A*B)

Y is false iff A AND B are true

– Typeset by FoilT EX – 7

FET-Based NAND Gate

GND Vcc A B A B F GND Vcc OFF OFF ON ON 1 1 1 1 GND Vcc 1 1 OFF ON OFF ON 1

– Typeset by FoilT EX – 8

NOR Gates

NOR A B F=(A + B)’ 1 1 1 1 1

A B Y = not(A + B)

A B Y = not(A or B)

OR

A B Y = A + B

Y is true if A OR B are true NOR

A B Y = not(A or B)

Y is false if A OR B are true

– Typeset by FoilT EX – 9

FET-based NOR Gate

GND Vcc A B A B F

A B F 0v 0v ? 0v 5v ? 5v 0v ? 5v 5v ? Can you complete the truth table?

– Typeset by FoilT EX – 10

FET-Based Gates

• P-type FETs must be on top of gate
• N-type FETs must be on bottom of gate

– Due to electrical characteristics of the two FET types

• Output is driven to either ’1’ or ’0’

– never both – never neither

– Typeset by FoilT EX – 11

Exclusive-OR (XOR)

Output is true if and only if inputs are different. A B Q = A ⊕ B 1 1 1 1 1 1

A B Q

Q = A ⊕ B = A’B + AB’ Another definition: Q is true if A = B.

– Typeset by FoilT EX – 12

Exclusive-OR Theorems

X ⊕ 0 = X X ⊕ 1 = X’ X ⊕ X = 0 X ⊕ X’ = 1 X ⊕ Y = Y ⊕ X Commutative law (X ⊕ Y) ⊕ Z = X ⊕ (Y ⊕ Z) = X ⊕ Y ⊕ Z Associative law (X ⊕ Y)’ = X ⊕ Y’ = X’ ⊕ Y The first four are important, the others are used less frequently.

– Typeset by FoilT EX – 13

Equivalence Operation

≡ denotes equivalence (also written as X==Y) Output is true if and only if inputs are equal X Y X ≡ Y 1 1 1 1 1 1

A B Q

Q = (X ≡ Y) = X’Y’ + XY

– Typeset by FoilT EX – 14

XOR and EQUIV are complements

X Y X ⊕ Y X ≡ Y 1 1 1 1 1 1 1 1 Alternate symbol

A B Q

Bubble means NOT. This gate is often called exclusive NOR or XNOR.

– Typeset by FoilT EX – 15

Multi-Input Gates

Vcc A B A F C B C GND

GND Vcc A B A B F

Which one will be slower/faster? Electricity moves at the speed

• f light.

– Typeset by FoilT EX – 16

Alternative Gate Symbols

The symbolic meaning of the circuit should be clear from what you draw. Alternative symbols can reduce some gate requirements.

– Typeset by FoilT EX – 17

Alternative Gate Symbols

A B Q

Q is true if A is false OR B is false.

A B Q

Q is true if and only if A is false and B is false.

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Alternative Gate Symbols

A B Q

Q is true if A is false OR B is false.

A B Q

Q is true if and only if A is false and B is false. X Y Q 1 1 1 1 1 1 1 X Y Q 1 1 1 1 1

Q A B

A B Q

– Typeset by FoilT EX – 19

Alternative Gate Symbols

Turn on sprinklers if it is not a holiday and it is not a weekend.

A B Q

• r?

A B Q

տ

The problem statement uses AND, so use the AND symbol.

– Typeset by FoilT EX – 20

Alternative Gate Symbols

Turn off sprinklers if it is a holiday or it is a weekend.

A B Q

• r?

A B Q

ր

The problem statement uses OR, so use the OR symbol.

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Another Example

Design a circuit to determine whether the bits of a 4-bit wire are all zero.

– Typeset by FoilT EX – 22

Another Example

Design a circuit to determine whether the bits of a 4-bit wire are all zero. This is the appropriate symbol to use.

– Typeset by FoilT EX – 23

Mixed Symbols

Q A B

Q is true iff A is false AND B is true

• Such a gate doesn’t likely exist
• Build from AND gate and inverter
• Simplifies schematics and enhanced readability

– Typeset by FoilT EX – 24

Single Gate Conversion Rules

• Change symbol

– AND to OR – OR to AND

• Invert all inputs and outputs
• No change in behavior – merely a symbol change

Q A B

A B Q

Q is true iff A is false AND B is true Q is false if A true OR B is false.

– Typeset by FoilT EX – 25

Alternative Gate Symbols - Summary

• Use the symbol that matches the problem statement

– Clarity – Documentation – Maintenance

• If

function is correct but symbol is wrong, then your schematic is wrong.

– Typeset by FoilT EX – 26

Positive vs Negative Logic

Gate Logic v3 v2 v1 vout

v1 v2 v3 vout 0v 0v 0v 0v 0v 0v 5v 0v 0v 5v 0v 0v 0v 5v 5v 0v 5v 0v 0v 0v 5v 0v 5v 0v 5v 5v 0v 0v 5v 5v 5v 5v

– Typeset by FoilT EX – 27

Positive Logic

Let: O volts → 0 5 volts → 1

v1 v2 v3 vout 0v 0v 0v 0v 0v 0v 5v 0v 0v 5v 0v 0v 0v 5v 5v 0v 5v 0v 0v 0v 5v 0v 5v 0v 5v 5v 0v 0v 5v 5v 5v 5v v1 v2 v3 vout 1 1 1 1 1 1 1 1 1 1 1 1 1

The circuit is a logical AND gate.

– Typeset by FoilT EX – 28

Negative Logic

Let: O volts → 1 5 volts → 0

v1 v2 v3 vout 0v 0v 0v 0v 0v 0v 5v 0v 0v 5v 0v 0v 0v 5v 5v 0v 5v 0v 0v 0v 5v 0v 5v 0v 5v 5v 0v 0v 5v 5v 5v 5v v1 v2 v3 vout 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

The same is a circuit logical OR gate.

– Typeset by FoilT EX – 29

Positive/Negative Logic

The most common mapping is: +V ⇐ ⇒ 1 0V ⇐ ⇒ 0 Different systems have used different mappings in the past.

– Typeset by FoilT EX – 30

Multi-Level Logic

– Typeset by FoilT EX – 31

Levels of a network

Maximum number of gates between an input and the output 5 Level In general, the more levels, the slower the circuit. 3 Level

– Typeset by FoilT EX – 32

Number of Levels

• Number of levels can be increased by factoring.

G = AB + ACDE + ACF = A(B+CDE+CF)

• Number of levels can be descreased by multiplying out..

G = A(B+CDE+CF) = AB + ACDE + ACF

– Typeset by FoilT EX – 33

Example

G = AB + ACDE + ACF

Levels = 2 #Gates = 4 Delay = tand4 + tor3 #Inputs = 12 #transistors = 24 Largest gate = 4 inputs

G A B C D E A C F A

Area calculations:

• each input to a gate costs 2 transistors
• area ∝ # of transistors

Delay calculations:

• find the slowest past from inputs to outputs

tdelay = tand4 + tor3

• the 4-input AND is likely slower than the
• ther AND gates.

– Typeset by FoilT EX – 34

Change the number of levels by factoring

G = ACDE + ACF + AB = A(CDE + CF + B) factor →

C D E C F B A G

This is a 3-level circuit.

Levels = 3 #Gates = 4 Delay = tand3 + tor3 + tand2 #Inputs = 10 #transistors = 20 Largest gate = 3 inputs

– Typeset by FoilT EX – 35

Factor Again

G = A(CDE + CF + B) = A(B+C(F+DE)) factor →

D E F C B A G

This is a 5-level circuit. Levels = 5 #Gates = 5 Delay = 3 × tand2 + 2 × tor2 #Inputs = 10 #transistors = 20 Largest gate = 2 inputs

– Typeset by FoilT EX – 36

Changing the number of levels

Three alternative solutions for the same function... 2-level 3-level 4-level Logic Levels 2 3 5 Delay

tand4 + tor3 tand3 + tor3 + tand2 3 × tand2 + 2 × tor2

Gate Count 4 4 5 Gate Inputs 12 10 10 Transistors 24 20 20 Largest gate 4 3 2 Each has different area/speed characteristics.

– Typeset by FoilT EX – 37

Two-Level vs. Multi-Level

• In general:

– two-level is fastest – multi-level can be smaller

• Exploring by hand to find just the right solution can be difficult
• We will focus on two-level

– easy to get from truth table – minimization techniques in later chapters focus on it

– Typeset by FoilT EX – 38