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Mixed Gates: Leakage Reduction Mixed Gates: Leakage Reduction - - PowerPoint PPT Presentation

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Mixed Gates: Leakage Reduction Mixed Gates: Leakage Reduction Techniques applied to Techniques applied to Switches for on- -chip Networks chip Networks Switches for on Frank Sill, Claas Cornelius, Stephan Kubisch, Dirk Timmermann Institute

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SLIDE 1

University of Rostock Institute of Applied Microelectronics and Computer Engineering 1 MG & Switch, Sill (ReCoSoC‘06)

Mixed Gates: Leakage Reduction Mixed Gates: Leakage Reduction Techniques applied to Techniques applied to Switches for on Switches for on-

  • chip Networks

chip Networks

Frank Sill, Claas Cornelius, Stephan Kubisch, Dirk Timmermann

Institute of Applied Microelectronics and Computer Engineering University of Rostock

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SLIDE 2

University of Rostock Institute of Applied Microelectronics and Computer Engineering 2 MG & Switch, Sill (ReCoSoC‘06)

Focus of this Work Focus of this Work

  • 1. Advancement of established Leakage Reduction

techniques (DVTCMOS / DTOCMOS)

  • 2. Application of the new approach to NOC Switches

DVTCMOS: Dual Vth CMOS DTOCMOS: Dual Tox CMOS NOC: Network-On-Chip

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SLIDE 3

University of Rostock Institute of Applied Microelectronics and Computer Engineering 3 MG & Switch, Sill (ReCoSoC‘06)

Outline Outline

  • 1. Motivation
  • 2. Basics
  • 3. Mixed Gates
  • 4. Leakage Reduction of NOC Switches
  • 5. Conclusion
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SLIDE 4

University of Rostock Institute of Applied Microelectronics and Computer Engineering 4 MG & Switch, Sill (ReCoSoC‘06)

Motivation Motivation

  • S. Borkar, ‘05
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SLIDE 5

University of Rostock Institute of Applied Microelectronics and Computer Engineering 5 MG & Switch, Sill (ReCoSoC‘06)

Motivation Motivation

  • S. Borkar, ‘05

Up to 50 % will be leakage!

SiO2 Lkg - Gate Oxide Tunneling Leakage (Igate) SD Lkg - Subthreshold Leakage (Isub)

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SLIDE 6

University of Rostock Institute of Applied Microelectronics and Computer Engineering 6 MG & Switch, Sill (ReCoSoC‘06)

  • 2. Basics
  • 2. Basics
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SLIDE 7

University of Rostock Institute of Applied Microelectronics and Computer Engineering 7 MG & Switch, Sill (ReCoSoC‘06)

Power Dissipation in CMOS Power Dissipation in CMOS

VDD GND CL Idyn Isc Isub Igate

  • Isub occurs if Vg < Vt
  • carriers move by diffusion along surface
  • Igate caused by direct tunneling through

gate oxide

SiO2

n+

Source Drain Gate

p - well

Igate Isub

n+ L

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SLIDE 8

University of Rostock Institute of Applied Microelectronics and Computer Engineering 8 MG & Switch, Sill (ReCoSoC‘06)

V Vth

th vs. Delay and Leakage

  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 250 m 270 m 290 m 310 m 330 m 350 m 370 m

Threshold Voltage VthNMOS [V] Leakage [A]

30 p 35 p 40 p 45 p 50 p 55 p

Delay [s]

Subthreshold Leakage Delay

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SLIDE 9

University of Rostock Institute of Applied Microelectronics and Computer Engineering 9 MG & Switch, Sill (ReCoSoC‘06)

V Vth

th vs. Delay and Leakage

  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 250 m 270 m 290 m 310 m 330 m 350 m 370 m

Threshold Voltage VthNMOS [V] Leakage [A]

30 p 35 p 40 p 45 p 50 p 55 p

Delay [s]

Subthreshold Leakage Delay fast ) slow

th)

devices with high power dissipation (low Vth

  • r

devices with low power dissipation (high V

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SLIDE 10

University of Rostock Institute of Applied Microelectronics and Computer Engineering 10 MG & Switch, Sill (ReCoSoC‘06)

T Tox

  • x vs. Delay and Leakage
  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 14 16 17 18 20 22

Thickness of gate oxide (Tox) [10-10m] Leakage [A]

25 p 30 p 35 p 40 p 45 p 50 p

Delay [s]

Delay Gate- Leakage

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SLIDE 11

University of Rostock Institute of Applied Microelectronics and Computer Engineering 11 MG & Switch, Sill (ReCoSoC‘06)

T Tox

  • x vs. Delay and Leakage
  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 14 16 17 18 20 22

Thickness of gate oxide (Tox) [10-10m] Leakage [A]

25 p 30 p 35 p 40 p 45 p 50 p

Delay [s]

Delay Gate- Leakage fast devices with high power dissipation (low Tox)

  • r

slow devices with low power dissipation (high Tox)

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SLIDE 12

University of Rostock Institute of Applied Microelectronics and Computer Engineering 12 MG & Switch, Sill (ReCoSoC‘06)

DVTCMOS / DTOCMOS DVTCMOS / DTOCMOS

Dual Threshold Voltages (DVTCMOS)

  • Use different Vth’s

– use lower threshold for devices within the critical paths – use higher threshold for devices outside the critical paths Dual Tox (DTOCMOS)

  • Use different Tox’s

– use thinner gate oxide for devices within the critical paths – use thicker gate oxide for devices outside the critical paths

Decrease leakage without performance penalty

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SLIDE 13

University of Rostock Institute of Applied Microelectronics and Computer Engineering 13 MG & Switch, Sill (ReCoSoC‘06)

DVTCMOS / DTOCMOS cont DVTCMOS / DTOCMOS cont’ ’d d

LVTO

(low Vth / Tox = fast, high leakage)

HVTO

(high Vth / Tox = slow, low leakage)

critical path

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SLIDE 14

University of Rostock Institute of Applied Microelectronics and Computer Engineering 14 MG & Switch, Sill (ReCoSoC‘06)

  • 3. Mixed Gates
  • 3. Mixed Gates
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SLIDE 15

University of Rostock Institute of Applied Microelectronics and Computer Engineering 15 MG & Switch, Sill (ReCoSoC‘06)

Goal (for fast gates): Preserve the delay while decreasing the leakage

Mixed Mixed-

  • V

Vth

th/T

/Tox

  • x Pull

Pull-

  • Down/Up

Down/Up-

  • Paths

Paths

R 2R 0 → 1 delay (Output from GND to VDD) VDD GND OUT

But: At timing analysis → only maximum delay is considered! delay0→1 < delay1 →0

1 → 0 delay (Output from VDD to GND) IN1 IN2

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SLIDE 16

University of Rostock Institute of Applied Microelectronics and Computer Engineering 16 MG & Switch, Sill (ReCoSoC‘06)

Mixed Mixed-

  • V

Vth

th/T

/Tox

  • x Pull

Pull-

  • Down/Up

Down/Up-

  • Paths Cont

Paths Cont’ ’d d

Idea: Use different Vth / Tox devices within a gate to adapt the delays

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SLIDE 17

University of Rostock Institute of Applied Microelectronics and Computer Engineering 17 MG & Switch, Sill (ReCoSoC‘06)

Mixed Mixed-

  • V

Vth

th/T

/Tox

  • x Pull

Pull-

  • Down/Up

Down/Up-

  • Paths Cont

Paths Cont’ ’d d

Idea: Use different Vth / Tox devices within a gate to adapt the delays

High - Vth/Tox

Low - Vth/Tox

delay0→1 = delay1 →0

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SLIDE 18

University of Rostock Institute of Applied Microelectronics and Computer Engineering 18 MG & Switch, Sill (ReCoSoC‘06)

Mixed Gates Mixed Gates

Goal: Additional gate types at constant mask count Only two gate types in DVTCMOS / DTOCMOS → Problem: More high leakage gates after optimization as needed to keep the delay Idea: Mixed Vth / Tox gates to increase the amount of possible gate types

High - Vth/Tox Low - Vth/Tox

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SLIDE 19

University of Rostock Institute of Applied Microelectronics and Computer Engineering 19 MG & Switch, Sill (ReCoSoC‘06)

Mixed Gates Mixed Gates -

  • NAND2

NAND2

LVTO gate

  • rise time is shorter

than fall time

  • minimum delay cell
  • very high leakage

F - MG gate

  • rise and fall time are

nearly the same

  • minimum delay cell
  • high leakage

MG gate

  • middle delay cell
  • middle leakage

HVTO gate

  • maximum delay cell
  • minimum leakage

Low - Vth/Tox High - Vth/Tox

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SLIDE 20

University of Rostock Institute of Applied Microelectronics and Computer Engineering 20 MG & Switch, Sill (ReCoSoC‘06)

  • 4. Leakage Reduction of
  • 4. Leakage Reduction of

NOC Switches NOC Switches

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SLIDE 21

University of Rostock Institute of Applied Microelectronics and Computer Engineering 21 MG & Switch, Sill (ReCoSoC‘06)

Network Network-

  • on
  • n-
  • Chip

Chip

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SLIDE 22

University of Rostock Institute of Applied Microelectronics and Computer Engineering 22 MG & Switch, Sill (ReCoSoC‘06)

Switch Switch – – Architecture Architecture

West- Port North- Port South- Port East- Port Control

(Arbiter, Switching)

L

  • c

a l P

  • r

t Resource

Bus width 16 Gate-Count 1,937 FF-Count 193 Frequency 337.6 MHz Pdyn 214.7 µW

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SLIDE 23

University of Rostock Institute of Applied Microelectronics and Computer Engineering 23 MG & Switch, Sill (ReCoSoC‘06)

Simulation Simulation Results Results

0% 20% 40% 60% 80%

1D-Switch 2x1D-Switch 2D-Switch c499

Leakage Reduction MG vs. LVTO MG vs. DVTO

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SLIDE 24

University of Rostock Institute of Applied Microelectronics and Computer Engineering 24 MG & Switch, Sill (ReCoSoC‘06)

  • 5. Conclusion
  • 5. Conclusion
  • Subthreshold current and gate oxide leakage

dominate leakage power

  • Mixed Gates approach combines advantages of

DVTCMOS and DTOCMOS at transistor and gate level

  • Average 83% (vs. LVTO) and 10% (vs. DVTO-

CMOS) leakage reduction at constant delay