Design of Mixed Gates for Design of Mixed Gates for Leakage - - PowerPoint PPT Presentation

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Design of Mixed Gates for Design of Mixed Gates for Leakage - - PowerPoint PPT Presentation

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GLSVLSI 2007 17th edition of ACM Great Lakes Symposium on VLSI Design of Mixed Gates for Design of Mixed Gates for Leakage Reduction Leakage Reduction Frank Sill, Jiaxi You, Dirk Timmermann Institute of Applied Microelectronics and Computer

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Design of Mixed Gates for Design of Mixed Gates for Leakage Reduction Leakage Reduction

Frank Sill, Jiaxi You, Dirk Timmermann

Institute of Applied Microelectronics and Computer Engineering University of Rostock, Germany

GLSVLSI 2007

17th edition of ACM Great Lakes Symposium on VLSI

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Focus of this Work Focus of this Work

  • 1. Advancement of established Leakage Reduction

techniques (DVTCMOS / DTOCMOS)

  • 2. Investigations on rules for Mixed Gates design

DVTCMOS: Dual Vth CMOS DTOCMOS: Dual Tox CMOS

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Outline Outline

  • 1. Motivation
  • 2. Basics
  • 3. Mixed Gates
  • 4. Design Rules
  • 5. Benchmark results
  • 6. Conclusions
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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Motivation Motivation

  • S. Borkar, ‘05
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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Motivation Motivation

  • S. Borkar, ‘05

Up to 50 % will be (is !) leakage!

SiO2 Lkg - Gate Oxide Tunneling Leakage (Igate) SD Lkg - Subthreshold Leakage (Isub)

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

  • 2. Basics
  • 2. Basics
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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Power Dissipation in CMOS Power Dissipation in CMOS

VDD GND CL Idyn Isc Isub Igate

  • Isub occurs if Vgs < Vth
  • carriers move by diffusion along surface
  • Igate caused by direct tunneling through

gate oxide

SiO2

n+

Source Drain Gate

p - well

Igate Isub

n+ L

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

V Vth

th vs. Delay and Leakage

  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 250 m 270 m 290 m 310 m 330 m 350 m 370 m

Threshold Voltage VthNMOS [V] Leakage [A]

30 p 35 p 40 p 45 p 50 p 55 p

Delay [s]

Subthreshold Leakage Delay

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

V Vth

th vs. Delay and Leakage

  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 250 m 270 m 290 m 310 m 330 m 350 m 370 m

Threshold Voltage VthNMOS [V] Leakage [A]

30 p 35 p 40 p 45 p 50 p 55 p

Delay [s]

Subthreshold Leakage Delay fast devices with high power dissipation (low Vth)

  • r

slow devices with low power dissipation (high Vth)

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Mixed Gates, Sill (GLSVLSI‘07)

T Tox

  • x vs. Delay and Leakage
  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 14 16 17 18 20 22

Thickness of gate oxide (Tox) [10-10m] Leakage [A]

25 p 30 p 35 p 40 p 45 p 50 p

Delay [s]

Delay Gate- Leakage

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

T Tox

  • x vs. Delay and Leakage
  • vs. Delay and Leakage

Inverter (BPTM 65 nm)

0 n 40 n 80 n 120 n 160 n 14 16 17 18 20 22

Thickness of gate oxide (Tox) [10-10m] Leakage [A]

25 p 30 p 35 p 40 p 45 p 50 p

Delay [s]

Delay Gate- Leakage fast devices with high power dissipation (low Tox)

  • r

slow devices with low power dissipation (high Tox)

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

DVTCMOS / DTOCMOS DVTCMOS / DTOCMOS

Dual Threshold Voltages (DVTCMOS)

  • Use different Vth’s

– use lower threshold for devices within the critical paths – use higher threshold for devices outside the critical paths Dual Tox (DTOCMOS)

  • Use different Tox’s

– use thinner gate oxide for devices within the critical paths – use thicker gate oxide for devices outside the critical paths

Decrease leakage without performance penalty

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

DVTCMOS / DTOCMOS cont DVTCMOS / DTOCMOS cont’ ’d d

LVTO

(low Vth / Tox = fast, high leakage)

HVTO

(high Vth / Tox = slow, low leakage)

critical path

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

  • 3. Mixed Gates
  • 3. Mixed Gates
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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Goal (for fast gates): Preserve the delay while decreasing the leakage

Mixed Mixed-

  • V

Vth

th/T

/Tox

  • x Pull

Pull-

  • Down/Up

Down/Up-

  • Paths

Paths

R 2R 0 → 1 delay (Output from GND to VDD) VDD GND OUT

But: At timing analysis → only maximum delay is considered! delay0→1 < delay1 →0

1 → 0 delay (Output from VDD to GND) IN1 IN2

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Mixed Mixed-

  • V

Vth

th/T

/Tox

  • x Pull

Pull-

  • Down/Up

Down/Up-

  • Paths Cont

Paths Cont’ ’d d

Idea: Use different Vth / Tox devices within a gate to adapt the delays

High - Vth/Tox

Low - Vth/Tox

delay0→1 = delay1 →0

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Mixed Gates Mixed Gates

Goal: Additional gate types at constant mask count Only two gate types in DVTCMOS / DTOCMOS → Problem: More high leakage gates after optimization as needed to keep the delay Idea: Mixed Vth / Tox gates to increase the amount of possible gate types

High - Vth/Tox Low - Vth/Tox

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Mixed Gates Mixed Gates -

  • NAND2

NAND2

HVTO gate

  • maximum delay cell
  • minimum leakage

MG gate

  • middle delay cell
  • middle leakage

F - MG gate

  • rise and fall time are

nearly the same

  • minimum delay cell
  • high leakage

LVTO gate

  • rise time is shorter

than fall time

  • minimum delay cell
  • very high leakage

Low - Vth/Tox High - Vth/Tox

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Mixed Gates, Sill (GLSVLSI‘07)

  • 4. Design Rules
  • 4. Design Rules
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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Design Rules Design Rules – – Why? Why?

  • With two different device types:

@2 input gate: at least 24 = 16 possibilities @3 input gate: at least 26 = 64 possibilities Design rules decrease library design time

  • Behavior of mixed stacks?
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Mixed Gates, Sill (GLSVLSI‘07)

Delay in Mixed Stacks Delay in Mixed Stacks

  • Two worst case scenarios:
  • Multi signal switch (MSS): all inputs switch

together

  • Single signal switch (SSS): only lowest signal

switches

  • Plateau-Phase [1]:
  • Internal voltages and current are constant
  • Dominates delay

[1] Bisdounis et al., Analytical Transient Response and Propagation Delay Evaluation of the CMOS Inverter for Short-channel Devices", In IEEE Journal of Solid-State Circuits, 33-2, 1998.

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Multi Signal Switch Multi Signal Switch

  • Plateau voltage Vpl depends on top transistor Ttop in stack (only Ttop is saturated)
  • Vpl determines current Istack through stack

Ttop has highest influence on delay @MMS

VDD CL Vout@MSS Vint Vin Out Vint@MSS VDD Ttop Tbottom Istack Vpl time

Plateau Phase

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Single Signal Switch Single Signal Switch

  • In start phase: internal voltages have to discharged
  • Tbottom has highest influence on Idiscarge

Ttop and Tbottom have highest influence on delay @SSS

Vout@SSS Vin Vint@SSS Vpl VDD VDD CL Vint Out Ttop Tbottom Cint Idischarge Istack Pleatau-Phase internal capacitances discharges time

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Leakage in Mixed Stack Leakage in Mixed Stack

Subthreshold leakage Isub

  • Isub depends on input vector (stack effect)

BUT: Positions of off-elements doesn’t matter Average Isub is depends only on amount of high-Vth/Tox elements Gate oxide leakage Igate

  • Tbottom connected with GND

Tbottom has highest average gate leakage Igate

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Design Rules for Mixed Stacks Design Rules for Mixed Stacks

Delay rule 1: If longest delay at MSS, then low-Vth/Tox as high as possible Delay rule 2: If longest delay at SSS, then at first Tbottom then Ttop is low-Vth/Tox Leakage rule: Lowest possible transistor is high-Vth/Tox Rules are applied at design phase, until desired delay is reached.

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

  • 5. Results
  • 5. Results
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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Example Example: NAND3 : NAND3 – – Mixed Stack Mixed Stack

Results compared to LVTO gates

NA3_HHH_LLH NA3_HHH_LHL NA3_HHH_LHH NA3_HHH_HLL NA3_HHH_HLH NA3_HHH_HHL NA3_HHH_HHH

40% 50% 60% 70% 80%

15% 20% 25% 30% 35%

Delay increase

Leakage decrease

  • ne High-Vth/Tox element

two High-Vth/Tox elements

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Benchmark results Benchmark results

  • Gate library:
  • 65 nm BPTM technology
  • 42 gates
  • for each gate LVTO, HVTO, F-MG, MG type
  • ISCAS benchmark designs (200 – 4000 gates)
  • Each design implemented with LVTO,

DVTCMOS/DTOCMOS, and Mixed Gates approach

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

LVTO vs. Mixed Gates @ ISCAS LVTO vs. Mixed Gates @ ISCAS

0% 10% 20% 30% 40% 50% 60% 70% 80% c432 c499 c880 c1335 c1908 c2610 c3540 c5315 c6288 c7552

Reduction of Leakage Currents

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

DTCMOS vs. Mixed Gates @ ISCAS DTCMOS vs. Mixed Gates @ ISCAS

0% 5% 10% 15% 20% 25% 30% 35% c432 c499 c880 c1335 c1908 c2610 c3540 c5315 c6288 c7552

Reduction of Leakage Currents

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

  • 5. Conclusions
  • 5. Conclusions
  • Mixed Gates approach combines advantages of

DVTCMOS and DTOCMOS at transistor and gate level

  • Proposed design rules ease library design phase
  • Average 65% (vs. LVTO) and 18% (vs. DVTO-

CMOS) leakage reduction at constant delay

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University of Rostock Institute of Applied Microelectronics and Computer Engineering

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Mixed Gates, Sill (GLSVLSI‘07)

Thank you! Thank you!

Contact: email: frank.sill@uni-rostock.de Tel.: +49 381 4987278