Foundations of Combinational Circuits Checking a Circuit Mapping - - PowerPoint PPT Presentation

• Foundations of

Combinational Circuits

Checking a Circuit

Mapping the circuit into a directed graph G(V,E).

• Each gate is a vertex
• Each output terminal defines a net
• Each net is transformed into edges from the output terminal to each of

the input terminals. OR AND NOT XOR OUT IN IN Single net

Graph Representation by List of Neighbors

6 7 8 3 4 5 2 1 3 5 8 6 7 5 6 2 8

Graph Representation by Matrix

v v v 5 4 3 2 1 5 4 3 2 1

Checking a Circuit

• If a terminal has two incoming edges, then

it is fed by two nets, which is illegal. In that case we stop and return FALSE.

OR AND NOT XOR OUT IN IN Two inputs to

• ne

terminal !

Testing for Circles

• In order to test for circles we need to run a

Depth-First-Search (DFS) algorithm on the graph, and check for any backwards edges during the execution of the algorithm.

DFS Example

1 2 4 5 3 Stack

DFS

1 1 2 4 5 3 Stack = Currently in the stack

DFS

1 2 1 2 4 5 3 Stack

DFS

1 2 3 1 2 4 5 3 Stack

DFS

1 2 3 1 2 4 5 3 4 Stack Backwards Edge This graph has a cycle!

Elements of the Proof

• The algorithm terminates regardless of the

structure of the input graph.

• If there is a cycle in the graph, the

algorithm will find it (return FALSE).

• If there is no cycle in the graph, the

algorithm will return TRUE.

The Algorithm Terminates

• The algorithm passes through every vertex
• nly once, therefore it will always

terminate after visiting all of the vertices regardless of the edges.

The Proof

• Assume there is a cycle in the graph. At

some point a first vertex that belongs to the cycle will be reached. All other vertices

• f the cycle have not been reached yet.
• Before that first vertex is popped out of the

stack, the DFS procedure guarantees that an edge closing the cycle and entering that vertex will be tested.

• It is a backwards edge.

The Proof

• Immediate, but nevertheless:
• Assume there are no cycles in the graph.
• Backwards edges cannot exist since they

require a path from a successor to a predecessor, which means there is a cycle.

Topological Sort

• Works only on Directed Acyclic Graphs (DAG).
• The Algorithm:

– Form a set of all independent vertices - those that have no incoming edges. There must be at least one! – While the set is empty: Pick any vertex v from the set. If any of its successors have no other predecessors – add them to the set of independent vertices. Erase all

• f the edges originating at v.

Topological Sort Example

OR AND NOT XOR OUT IN IN = Independent Vertex

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN IN

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN IN OR

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN IN OR AND

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN IN OR AND NOT

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN IN OR AND NOT XOR

Topological Sort Example

OR AND NOT XOR OUT IN IN The Topological Sort: IN IN OR AND NOT XOR OUT

Testing for Cycles during Topological Sort

OR AND NOT XOR OUT IN IN

There are nodes left, but none are independent Cycle!

Propagation Delay

} {

pd paths all pd

t Max

T

=

There is always at least one “critical path”. What is the propagation delay of a circuit that is not acyclic?

Finding the Propagation Delay

)} ' ( ) ' ( { ) (

) ( '

v t v t Max v t

pd ready inputs v r predecesso v ready inputs

+ =

∈

Now, using the fact that it is an acyclic graph, we go through the topological order from start to beginning, each time updating the “inputs ready” time of the successors. The total propagation delay is the maximal “inputs ready” time (assuming that we used output nodes).

Finding the Maximum Delay

OR AND NOT XOR OUT

A circuit with 2n/2 paths

2 options 2 options

n/2 stages with 2 options each, resulting in 2n/2 paths.

How are we computing the delay of an exponential number of circuits in linear time? Let’s go to the previous slide.

A circuit with 2n paths

• …cannot be built!
• Why? A combinational circuit is a DAG,

therefore we cannot reorder the gates to create different paths. Our only option is to include or exclude gates to create different paths.

• But, having n gates, we only have 2n such paths.

Each gate can be included or excluded, therefore 2n.

• We cannot build this circuit since we will require

an unbounded in-degree of the gates.

XOR is Associative – part I

c b a ab c b a ab c b a XOR XOR ) ' ' ( ' ) ' ' ( ) ), , ( ( + + + =

) ' ' ( ) , ( b a ab b a XOR + = c b a ab c b a ab ) ' ' ( ' ) ' ' ( ⋅ + + =

c b a b a c b a ab ) ' )( ' ( ' ) ' ' ( + + + + = c bb b a ba a a c b a ab ) ' ' ' ' ( ' ) ' ' ( + + + + + =

c b a ab c b a ab ) ' ' ( ' ) ' ' ( + + + = c b a abc bc a c ab ' ' ' ' ' ' + + + =

Definition 1st Expanded definition De Morgan De Morgan Distributive Complement Distributive

XOR is Associative – part 2

) ' ' ( ' ) ' ' ( )) , ( , ( c b bc a c b bc a c b XOR a XOR + + + =

) ' ' ( ) , ( b a ab b a XOR + =

) ' ' ( ' ) ' ' ( c b bc a c b bc a + + ⋅ =

) ' ' ( ' ) ' )( ' ( c b bc a c b c b a + + + + = ) ' ' ( ' ) ' ' ' ' ( c b bc a cc c b cb b b a + + + + + =

) ' ' ( ' ) ' ' ( c b bc a c b cb a + + + = c b a bc a c ab acb ' ' ' ' ' ' + + + =

Definition 2nd Expanded definition De Morgan De Morgan Distributive Complement Distributive

THE END