FE FELI LIX Tes est Fi Firmware Purpos ose type with Hit - - PowerPoint PPT Presentation

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FE FELI LIX Tes est Fi Firmware Purpos ose type with Hit - - PowerPoint PPT Presentation

FE FELI LIX Tes est Fi Firmware Purpos ose type with Hit Finding/Hit Finding Emulator Com ompatible inter erface ty Add FELIX bloc ock hea eader er and chunk trailer er - Compatible with FELIX FULLMODE data - Identify


slide-1
SLIDE 1

FE FELI LIX Tes est Fi Firmware Purpos

  • se
  • Com
  • mpatible inter

erface ty type with Hit Finding/Hit Finding Emulator

  • Add FELIX bloc
  • ck hea

eader er and chunk trailer er

  • Compatible with FELIX FULLMODE data
  • Identify link-number, chunk number, and data transfer integrity

1

slide-2
SLIDE 2

Inter erface e For

  • rmat: AX

AXI4-strea eam

2

From Karol’s documents

slide-3
SLIDE 3

FE FELI LIX Tes est Fi Firmware

  • Tes

est Data Gen ener erator

  • r
  • One generator for each link
  • AXI-Stream 32-bit interface
  • Only axis-tdata and axis-valid

are used currently

§ Axis-tuser, axis-tkeep and axis-tlast are not used

  • Data unit: 32-bit
  • Can be

e improv

  • ved

ed later er

3

  • SOP & EOP Inser

ert

  • Insert start-of-package and end-of-

package

  • Minimum invalid data between two

data packages: two 32-bit data

Tes est Data Gen ener erator

  • r can be

e rep eplaced ed by Hi Hit Finding or

  • r Hit Finding Emulator
  • r

(Half of FW: One PCIe endpoint)

slide-4
SLIDE 4

Tes est Data for

  • r Extra DMA

4

FELIX Block Header FELIX Chunk Trailer

0xXXXX 0x1111

Test Data:

0xXXXX: counter data Chunk size: 10

slide-5
SLIDE 5

Simplified ed FELIX FW on

  • nly with PCIe

e Inter erface

  • Most modules are commented out in the FELIX Top module.
  • The FELIX FW can be compiled with top vhdl file replaced only.
  • PCIe registers can be read and write using fpep

epo tool.

  • fl

flx-con

  • nfig lis

list tool to show registers

5

Reg egister er rea ead Reg egister er write Rea ead write/ e/ rea ead on

  • nly flag

Reg egister er addres ess Va Valid bits

The vhdl top file and bit file are shared in the link below: https://cernbox.cern.ch/index.php/s/4W5noFM7diMC2pp

slide-6
SLIDE 6

Su Summary

  • Dual to-host DMA descriptors transfer has been verified.
  • DMA-0: 5 links of normal WIB data
  • DMA-1: 5 links of hit finding data
  • Central Router for hit finding data has been verified.
  • AXI-Stream interface

§ Data unit: 32-bit § At least two 32-bit data between two valid data packages

  • Add block header and chunk trailer
  • Test data generator has been developed for test purpose.
  • Can be

e rep eplaced ed by Hit Finding or

  • r Hit Finding Emulator
  • r
  • A simplified

ed FW has been een built and tes ested ed.

  • Only with PCIe interface
  • Registers read and write via fpep

epo

6